Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
154 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
173 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
246 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
324 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
325 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
326 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
373 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
374 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
393 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
395 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
397 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
399 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
410 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
411 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
412 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
413 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
417 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
419 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
420 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
421 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
425 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
426 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
430 * Bank 4 - 5
434 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
435 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
436 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
437 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
438 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
439 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
440 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
564 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
566 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
568 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
570 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
572 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
574 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
585 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
588 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
591 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
603 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
604 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
605 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
627 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
642 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
678 /* TXA_TEST 8 bit Tx Arbiter Test Register */
680 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
681 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
682 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
683 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
684 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
685 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
688 /* TXA_STAT 8 bit Tx Arbiter Status Register */
699 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
700 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
701 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
702 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
722 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
724 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
725 CSR_START = 1<<4, /* Start Rx/Tx Queue */
742 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
768 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
770 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
813 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
814 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
815 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
817 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
818 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
819 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
821 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
822 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
823 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
973 * Marvel-PHY Registers, indirect addressed over GMAC
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1015 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1027 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1028 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1029 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1134 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1166 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1177 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1223 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1324 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1333 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1338 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1355 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1360 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1361 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1363 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1387 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1427 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1428 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1437 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1442 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1443 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1465 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1478 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1479 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1510 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1523 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1533 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1546 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1598 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1641 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1643 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1646 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1648 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1661 * MIB Counters base address definitions (low word) -
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1695 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1703 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1704 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1705 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1706 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1707 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1708 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1719 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1732 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1734 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1735 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1736 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1737 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1738 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1765 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1766 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1790 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1791 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1792 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1872 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1878 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1879 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1880 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1914 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1919 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1940 /* auto-negotiation with limited advertised speeds */
2020 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2021 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2022 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2028 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2048 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2050 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2057 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2058 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2059 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2060 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2061 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2062 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2063 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2064 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2065 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2066 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2067 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2068 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2069 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2070 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2113 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2118 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2120 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2121 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2127 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2133 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2137 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2141 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2155 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2156 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2157 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2187 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2190 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2204 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2205 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2206 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2208 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2211 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2214 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2217 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2245 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2260 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2272 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2273 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2274 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2285 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2287 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2289 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2330 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2331 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2338 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2339 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2340 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2341 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2342 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2343 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2344 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2345 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2346 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2347 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2348 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2349 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2351 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2352 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2353 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2354 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2355 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2356 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2357 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2358 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2478 return readl(hw->regs + reg); in skge_read32()
2483 return readw(hw->regs + reg); in skge_read16()
2488 return readb(hw->regs + reg); in skge_read8()
2493 writel(val, hw->regs + reg); in skge_write32()
2498 writew(val, hw->regs + reg); in skge_write16()
2503 writeb(val, hw->regs + reg); in skge_write8()
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))