Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
69 #define PAR_ENA 0x1 /* Parity Enable */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
89 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
92 #define TxENAB 0x8 /* Tx Enable */
94 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
95 #define Tx7 0x20 /* Tx 7 bits/character */
96 #define Tx6 0x40 /* Tx 6 bits/character */
97 #define Tx8 0x60 /* Tx 8 bits/character */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
110 #define MIE 8 /* Master Interrupt Enable */
150 #define BRENABL 1 /* Baud rate generator enable */
168 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
175 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
179 #define TxEOM 0x40 /* Tx underrun */
199 /* Read Register 2 (channel b only) - Interrupt vector */
203 #define CHBTxIP 0x2 /* Channel B Tx IP */
206 #define CHATxIP 0x10 /* Channel A Tx IP */
226 #define AUTOTXF 0x01 /* Auto Tx Flag */
233 #define TXFIFOE 0x20 /* Z85230: Int on TX FIFO completely empty */
237 #define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
238 #define FIFOE 4 /* FIFO Enable */