Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
18 #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */
19 #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */
31 #define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
32 #define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
39 #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */
42 #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */
43 #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */
44 #define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */
49 #define B43_PHY_HT_TXPCTL_IDLE_TSSI 0x1E9 /* TX power control idle TSSI */
55 #define B43_PHY_HT_TXPCTL_TARG_PWR 0x1EA /* TX power control target power */
102 #define B43_PHY_HT_TXPCTL_IDLE_TSSI2 B43_PHY_EXTG(0x165) /* TX power control idle TSSI */
105 #define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */