Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
20 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
23 #define AACI_IE 0x010 /* 7 bits Int Enable */
36 #define AACI_SLIEN 0x070 /* slot interrupt enable */
49 * TX/RX fifo control register (CR). P48
51 #define CR_FEN (1 << 16) /* fifo enable */
69 #define CR_EN (1 << 0) /* transmit enable */
76 #define SR_TXU (1 << 9) /* tx underrun */
78 #define SR_TXB (1 << 7) /* tx busy */
80 #define SR_TXFF (1 << 5) /* tx fifo full */
82 #define SR_TXHE (1 << 3) /* tx fifo half empty */
84 #define SR_TXFE (1 << 1) /* tx fifo empty */
91 #define ISR_URINTR (1 << 5) /* tx underflow */
94 #define ISR_TXINTR (1 << 2) /* tx fifo intr */
95 #define ISR_RXTOINTR (1 << 1) /* tx timeout */
96 #define ISR_TXCINTR (1 << 0) /* tx complete */
99 * interrupt enable register bits.
113 #define ISR_UR (1 << 5) /* tx fifo underrun */
116 #define ISR_TX (1 << 2) /* tx interrupt status */
118 #define ISR_TXC (1 << 0) /* tx complete */
121 * interrupt enable. P52
124 #define IE_UR (1 << 5) /* tx fifo underrun */
127 #define IE_TX (1 << 2) /* tx interrupt status */
129 #define IE_TXC (1 << 0) /* tx complete */
134 #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
136 #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */
138 #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */
140 #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */
142 #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */
144 #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */
146 #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */
170 #define MAINCR_DMAEN (1 << 9) /* dma enable */
171 #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
172 #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
173 #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
174 #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
175 #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
176 #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
179 #define MAINCR_IE (1 << 0) /* aaci interface enable */