Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
22 // above are used internally to indicate that we must enable access
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
32 #define IER 1 // ! Interrupt Enable Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
57 #define IER_RX 0x01 // Enable receive interrupt
58 #define IER_TX 0x02 // Enable transmit interrupt
59 #define IER_RXS 0x04 // Enable receive status interrupt
60 #define IER_MDM 0x08 // Enable modem status interrupt
61 #define IER_SLEEP 0x10 // Enable sleep mode
62 #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt
63 #define IER_RTS 0x40 // Enable RTS interrupt
64 #define IER_CTS 0x80 // Enable CTS interrupt
65 #define IER_ENABLE_ALL 0xFF // Enable all ints
68 #define FCR_FIFO_EN 0x01 // Enable FIFOs
70 #define FCR_TXCLR 0x04 // Reset Tx FIFO
71 #define FCR_DMA_BLK 0x08 // Enable DMA block mode
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
73 #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes
74 #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes
75 #define FCR_TX_LEVEL_32 0x20 // Tx FIFO Level = 32 bytes
76 #define FCR_TX_LEVEL_56 0x30 // Tx FIFO Level = 56 bytes
86 #define ISR_INT_TXRDY 0x02 // Tx ready int pending
104 #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char)
115 #define LCR_DL_ENABLE 0x80 // Enable access to divisor latch
118 // and also the '654-only registers
125 #define MCR_MASTER_IE 0x08 // Enable interrupt outputs
127 #define MCR_XON_ANY 0x20 // Enable any char to exit XOFF mode
128 #define MCR_IR_ENABLE 0x40 // Enable IrDA functions
137 #define LSR_TX_EMPTY 0x20 // Tx Fifo empty
138 #define LSR_TX_ALL_EMPTY 0x40 // Tx Fifo and shift register empty
144 #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1
153 // Tx Rx
154 //-------------------------------
173 #define EFR_TX_FC_NONE 0x00 // No Tx Xon/Xoff flow control
186 #define EFR_ENABLE_16654 0x10 // Enable 16C654 features
187 #define EFR_SPEC_DETECT 0x20 // Enable special character detect interrupt
189 #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control