Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
24 #define UART_IER 1 /* Out: Interrupt Enable Register */
25 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
26 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
28 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
32 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
49 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
55 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
107 #define UART_LCR_PARITY 0x08 /* Parity Enable */
124 #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
125 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
135 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
193 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
215 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
216 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
217 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
218 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
219 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
228 #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
232 * The Intel XScale on-chip UARTs define these bits
234 #define UART_IER_DMAE 0x80 /* DMA Requests Enable */
235 #define UART_IER_UUE 0x40 /* UART Unit Enable */
236 #define UART_IER_NRZE 0x20 /* NRZ coding Enable */
237 #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
268 #define UART_NMR 0x0D /* Nine-bit Mode Register */
277 #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
278 #define UART_ACR_ICRRD 0x40 /* ICR Read enable */
279 #define UART_ACR_ASREN 0x80 /* Additional status enable */
284 * These definitions are for the RSA-DV II/S card, from
286 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
289 #define UART_RSA_BASE (-8)
294 #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
295 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
298 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
300 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
301 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
302 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
303 #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
304 #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
308 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
309 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
310 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
336 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
337 #define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */
338 #define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */
356 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
357 #define UART_OMAP_TX_LVL 0x1a /* TX FIFO level register */
364 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
376 #define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */
377 #define UART_ALTR_TX_LOW 0x41 /* Tx FIFO Low Watermark */