Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
103 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
108 #define RxENABLE 0x1 /* Rx Enable */
111 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
121 #define PAR_ENA 0x1 /* Parity Enable */
124 #define SYNC_ENAB 0 /* Sync Modes Enable */
142 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
145 #define TxENAB 0x8 /* Tx Enable */
147 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
148 #define Tx7 0x20 /* Tx 7 bits/character */
149 #define Tx6 0x40 /* Tx 6 bits/character */
150 #define Tx8 0x60 /* Tx 8 bits/character */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
164 #define MIE 8 /* Master Interrupt Enable */
205 #define BRENABL 1 /* Baud rate generator enable */
219 #define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
224 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
231 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
235 #define TxEOM 0x40 /* Tx underrun */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B). */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only). */
261 #define CHBTxIP 0x2 /* Channel B Tx IP */
264 #define CHATxIP 0x10 /* Channel A Tx IP */