| /Zephyr-latest/drivers/spi/ |
| D | spi_grlib_spimctrl.c | 38 volatile struct spimctrl_regs *regs; member
104 volatile struct spimctrl_regs *const regs = cfg->regs; in transceive() local
120 regs->ctrl |= (CTRL_USRC | CTRL_IEN); in transceive()
121 regs->ctrl &= ~CTRL_CSN; in transceive()
130 regs->tx = txval; in transceive()
134 regs->ctrl |= CTRL_CSN; in transceive()
135 regs->ctrl &= ~CTRL_USRC; in transceive()
161 volatile struct spimctrl_regs *const regs = cfg->regs; in spim_isr() local
166 if ((regs->stat & STAT_DONE) == 0) { in spim_isr()
170 regs->stat = STAT_DONE; in spim_isr()
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| D | spi_sam0.c | 27 SercomSpi *regs; member
56 static void wait_synchronization(SercomSpi *regs) in wait_synchronization() argument
60 while ((regs->SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_MASK) != 0) { in wait_synchronization()
64 while ((regs->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
76 SercomSpi *regs = cfg->regs; in spi_sam0_configure() local
132 if (regs->CTRLA.reg != ctrla.reg || regs->CTRLB.reg != ctrlb.reg || in spi_sam0_configure()
133 regs->BAUD.reg != div) { in spi_sam0_configure()
134 regs->CTRLA.bit.ENABLE = 0; in spi_sam0_configure()
135 wait_synchronization(regs); in spi_sam0_configure()
137 regs->CTRLB = ctrlb; in spi_sam0_configure()
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| D | spi_sam.c | 36 Spi *regs; member
99 Spi *regs = cfg->regs; in spi_sam_configure() local
153 regs->SPI_CR = SPI_CR_SPIDIS; /* Disable SPI */ in spi_sam_configure()
154 regs->SPI_MR = spi_mr; in spi_sam_configure()
155 regs->SPI_CSR[spi_csr_idx] = spi_csr; in spi_sam_configure()
156 regs->SPI_CR = SPI_CR_SPIEN; /* Enable SPI */ in spi_sam_configure()
164 static void spi_sam_finish(Spi *regs) in spi_sam_finish() argument
166 while ((regs->SPI_SR & SPI_SR_TXEMPTY) == 0) { in spi_sam_finish()
169 while (regs->SPI_SR & SPI_SR_RDRF) { in spi_sam_finish()
170 (void)regs->SPI_RDR; in spi_sam_finish()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_opentitan.c | 24 uintptr_t regs; member
36 volatile uintptr_t regs = cfg->regs; in ot_aontimer_setup() local
38 sys_write32(0, regs + OT_REG_WDOG_COUNT_OFFSET); in ot_aontimer_setup()
39 sys_write32(1, regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_setup()
42 (void) sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_setup()
43 sys_write32(0, regs + OT_REG_WDOG_REGWEN_OFFSET); in ot_aontimer_setup()
51 volatile uintptr_t regs = cfg->regs; in ot_aontimer_disable() local
53 if (!sys_read32(regs + OT_REG_WDOG_REGWEN_OFFSET)) { in ot_aontimer_disable()
58 uint32_t ctrl_val = sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_disable()
63 sys_write32(ctrl_val & ~BIT(0), regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_disable()
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| /Zephyr-latest/drivers/dac/ |
| D | dac_sam0.c | 28 Dac *regs; member
40 Dac *regs = cfg->regs; in dac_sam0_write_value() local
47 regs->DATA.reg = (uint16_t)value; in dac_sam0_write_value()
77 Dac *regs = cfg->regs; in dac_sam0_init() local
93 regs->CTRLA.bit.SWRST = 1; in dac_sam0_init()
94 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
97 regs->CTRLB.bit.REFSEL = cfg->refsel; in dac_sam0_init()
98 regs->CTRLB.bit.EOEN = 1; in dac_sam0_init()
101 regs->CTRLA.bit.ENABLE = 1; in dac_sam0_init()
102 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | device_power.c | 75 struct ecia_named_regs *regs = ECIA_XEC_REG_BASE; in soc_deep_sleep_non_wake_en() local
77 regs->GIRQ22.SRC = UINT32_MAX; in soc_deep_sleep_non_wake_en()
78 regs->GIRQ22.EN_SET = MCHP_ESPI_WK_CLK_GIRQ_BIT; in soc_deep_sleep_non_wake_en()
85 struct ecia_named_regs *regs = ECIA_XEC_REG_BASE; in soc_deep_sleep_non_wake_dis() local
87 regs->GIRQ22.EN_CLR = UINT32_MAX; in soc_deep_sleep_non_wake_dis()
88 regs->GIRQ22.SRC = UINT32_MAX; in soc_deep_sleep_non_wake_dis()
97 struct ecia_named_regs *regs = ECIA_XEC_REG_BASE; in soc_deep_sleep_wake_en() local
100 regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT; in soc_deep_sleep_wake_en()
101 regs->GIRQ21.EN_SET = MCHP_KEYSCAN_GIRQ_BIT; in soc_deep_sleep_wake_en()
105 regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT; in soc_deep_sleep_wake_en()
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| /Zephyr-latest/soc/intel/intel_adsp/common/ |
| D | ipc.c | 44 volatile struct intel_adsp_ipc *regs = config->regs; in z_intel_adsp_ipc_isr() local
47 if (regs->tdr & INTEL_ADSP_IPC_BUSY) { in z_intel_adsp_ipc_isr()
51 uint32_t msg = regs->tdr & ~INTEL_ADSP_IPC_BUSY; in z_intel_adsp_ipc_isr()
52 uint32_t ext = regs->tdd; in z_intel_adsp_ipc_isr()
57 regs->tdr = INTEL_ADSP_IPC_BUSY; in z_intel_adsp_ipc_isr()
60 regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; in z_intel_adsp_ipc_isr()
62 regs->tda = INTEL_ADSP_IPC_DONE; in z_intel_adsp_ipc_isr()
68 bool done = (regs->ida & INTEL_ADSP_IPC_DONE); in z_intel_adsp_ipc_isr()
89 regs->ida = INTEL_ADSP_IPC_DONE; in z_intel_adsp_ipc_isr()
108 config->regs->tdr = INTEL_ADSP_IPC_BUSY; in intel_adsp_ipc_init()
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_sam0.c | 26 PortGroup *regs; member
56 PortGroup *regs = config->regs; in gpio_sam0_config() local
76 regs->OUTCLR.reg = BIT(pin); in gpio_sam0_config()
78 regs->OUTSET.reg = BIT(pin); in gpio_sam0_config()
80 regs->DIRSET.reg = BIT(pin); in gpio_sam0_config()
83 regs->DIRCLR.reg = BIT(pin); in gpio_sam0_config()
89 regs->OUTSET.reg = BIT(pin); in gpio_sam0_config()
91 regs->OUTCLR.reg = BIT(pin); in gpio_sam0_config()
102 regs->PINCFG[pin] = pincfg; in gpio_sam0_config()
112 *value = config->regs->IN.reg; in gpio_sam0_port_get_raw()
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| D | wch_gpio_ch32v00x.c | 19 GPIO_TypeDef *regs; member
31 GPIO_TypeDef *regs = config->regs; in gpio_ch32v00x_configure() local
56 regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin)); in gpio_ch32v00x_configure()
57 regs->BSHR = bshr; in gpio_ch32v00x_configure()
66 *value = config->regs->INDR; in gpio_ch32v00x_port_get_raw()
76 config->regs->BSHR = ((~value & mask) << 16) | (value & mask); in gpio_ch32v00x_port_set_masked_raw()
85 config->regs->BSHR = pins; in gpio_ch32v00x_port_set_bits_raw()
94 config->regs->BCR = pins; in gpio_ch32v00x_port_clear_bits_raw()
102 uint32_t changed = (config->regs->OUTDR ^ pins) & pins; in gpio_ch32v00x_port_toggle_bits()
104 config->regs->BSHR = (changed & pins) | (~changed & pins) << 16; in gpio_ch32v00x_port_toggle_bits()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_mchp_xec_v2.c | 147 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_ctl_wr() local
150 regs->CTRLSTS = ctrl; in i2c_ctl_wr()
152 regs->BLKID = ctrl; in i2c_ctl_wr()
164 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in wait_bus_free() local
169 sts = regs->CTRLSTS; in wait_bus_free()
207 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in get_lines() local
208 uint8_t port = regs->CFG & MCHP_I2C_SMB_CFG_PORT_SEL_MASK; in get_lines()
222 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_xec_reset_config() local
230 regs->CFG = MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO | in i2c_xec_reset_config()
249 regs->OWN_ADDR = EC_OWN_I2C_ADDR | (EC_OWN_I2C_ADDR << 8); in i2c_xec_reset_config()
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_gpio.h | 88 Gpio *regs; /** pointer to registers of the GPIO controller */ member
90 Pio *regs; /** pointer to registers of the PIO controller */ member
143 pin->regs->OVRS = pin->mask; in soc_gpio_set()
145 pin->regs->PIO_SODR = pin->mask; in soc_gpio_set()
161 pin->regs->OVRC = pin->mask; in soc_gpio_clear()
163 pin->regs->PIO_CODR = pin->mask; in soc_gpio_clear()
179 return pin->regs->PVR & pin->mask; in soc_gpio_get()
181 return pin->regs->PIO_PDSR & pin->mask; in soc_gpio_get()
209 pin->regs->STERS = pin->mask; in soc_gpio_debounce_length_set()
211 pin->regs->STERC = pin->mask; in soc_gpio_debounce_length_set()
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| /Zephyr-latest/tests/drivers/ipm/src/ |
| D | ipm_dummy.c | 32 if (!driver_data->regs.enabled || !driver_data->regs.busy) { in ipm_dummy_isr()
38 driver_data->cb_context, driver_data->regs.id, in ipm_dummy_isr()
39 (volatile void *)&driver_data->regs.data); in ipm_dummy_isr()
41 driver_data->regs.busy = 0U; in ipm_dummy_isr()
60 if (driver_data->regs.busy) { in ipm_dummy_send()
65 datareg = (volatile uint8_t *)driver_data->regs.data; in ipm_dummy_send()
70 driver_data->regs.id = id; in ipm_dummy_send()
71 driver_data->regs.busy = 1U; in ipm_dummy_send()
76 while (driver_data->regs.busy) { in ipm_dummy_send()
98 driver_data->regs.enabled = enable; in ipm_dummy_set_enabled()
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_xmc4xxx.c | 111 ETH_GLOBAL_TypeDef *regs; member
143 dev_cfg->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&tx_dma_desc[0]; in eth_xmc4xxx_tx_dma_descriptors_init()
162 dev_cfg->regs->OPERATION_MODE &= ~ETH_OPERATION_MODE_SR_Msk; in eth_xmc4xxx_flush_rx()
168 dev_cfg->regs->OPERATION_MODE |= ETH_OPERATION_MODE_SR_Msk; in eth_xmc4xxx_flush_rx()
184 dev_cfg->regs->OPERATION_MODE &= ~ETH_OPERATION_MODE_ST_Msk; in eth_xmc4xxx_flush_tx()
203 dev_cfg->regs->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk; in eth_xmc4xxx_flush_tx()
212 static inline void eth_xmc4xxx_trigger_dma_tx(ETH_GLOBAL_TypeDef *regs) in eth_xmc4xxx_trigger_dma_tx() argument
214 regs->STATUS = ETH_STATUS_TPS_Msk; in eth_xmc4xxx_trigger_dma_tx()
215 regs->TRANSMIT_POLL_DEMAND = 0; in eth_xmc4xxx_trigger_dma_tx()
218 static inline void eth_xmc4xxx_trigger_dma_rx(ETH_GLOBAL_TypeDef *regs) in eth_xmc4xxx_trigger_dma_rx() argument
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| /Zephyr-latest/drivers/serial/ |
| D | uart_sam0.c | 34 SercomUsart *regs; member
142 SercomUsart * const regs = cfg->regs; in uart_sam0_dma_tx_done() local
144 regs->INTENSET.reg = SERCOM_USART_INTENSET_TXC; in uart_sam0_dma_tx_done()
231 SercomUsart * const regs = cfg->regs; in uart_sam0_dma_rx_done() local
276 (uint32_t)(&(regs->DATA.reg)), in uart_sam0_dma_rx_done()
287 regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC; in uart_sam0_dma_rx_done()
310 SercomUsart * const regs = cfg->regs; in uart_sam0_rx_timeout() local
342 (uint32_t)(&(regs->DATA.reg)), in uart_sam0_rx_timeout()
347 regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC; in uart_sam0_rx_timeout()
397 SercomUsart * const usart = cfg->regs; in uart_sam0_configure()
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| D | uart_max32.c | 20 mxc_uart_regs_t *regs; member
48 MXC_UART_WriteCharacter(cfg->regs, c); in api_poll_out()
56 val = MXC_UART_ReadCharacterRaw(cfg->regs); in api_poll_in()
72 flags = MXC_UART_GetFlags(cfg->regs); in api_err_check()
93 mxc_uart_regs_t *regs = cfg->regs; in api_configure() local
130 err = MXC_UART_SetParity(regs, mxc_parity); in api_configure()
143 err = MXC_UART_SetStopBits(regs, MXC_UART_STOP_1); in api_configure()
145 err = MXC_UART_SetStopBits(regs, MXC_UART_STOP_2); in api_configure()
163 err = MXC_UART_SetDataSize(regs, (5 + uart_cfg->data_bits)); in api_configure()
186 err = Wrap_MXC_UART_SetFrequency(regs, uart_cfg->baudrate, cfg->perclk.clk_src); in api_configure()
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32h7x.c | 68 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in write_optb() local
71 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { in write_optb()
76 if ((regs->OPTCR & mask) == value) { in write_optb()
87 regs->OPTCR = (regs->OPTCR & ~mask) | value; in write_optb()
89 regs->OPTCR |= FLASH_OPTCR_PG_OPT; in write_optb()
91 regs->OPTCR |= FLASH_OPTCR_OPTSTART; in write_optb()
108 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_get_rdp_level() local
110 return (regs->OPTSR_CUR & FLASH_OPTSR_RDP_Msk) >> FLASH_OPTSR_RDP_Pos; in flash_stm32_get_rdp_level()
122 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_option_bytes_lock() local
125 regs->OPTCR |= FLASH_OPTCR_OPTLOCK; in flash_stm32_option_bytes_lock()
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_wch_afio.c | 27 GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port]; in pinctrl_configure_pins() local
47 regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4)); in pinctrl_configure_pins()
50 regs->OUTDR |= BIT(pin); in pinctrl_configure_pins()
51 regs->BSHR |= BIT(pin); in pinctrl_configure_pins()
53 regs->OUTDR |= BIT(pin); in pinctrl_configure_pins()
55 regs->BSHR |= BIT(pin + 16); in pinctrl_configure_pins()
57 regs->OUTDR &= ~(1 << pin); in pinctrl_configure_pins()
59 regs->BSHR = BIT(pin); in pinctrl_configure_pins()
62 regs->BCR = BIT(pin); in pinctrl_configure_pins()
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| /Zephyr-latest/drivers/counter/ |
| D | counter_max32_timer.c | 33 mxc_tmr_regs_t *regs; member
46 Wrap_MXC_TMR_EnableInt(cfg->regs); in api_start()
47 MXC_TMR_Start(cfg->regs); in api_start()
56 Wrap_MXC_TMR_DisableInt(cfg->regs); in api_stop()
57 MXC_TMR_Stop(cfg->regs); in api_stop()
66 *ticks = MXC_TMR_GetCount(cfg->regs); in api_get_value()
89 return Wrap_MXC_TMR_GetPendingInt(cfg->regs); in api_get_pending_int()
110 mxc_tmr_regs_t *regs = config->regs; in set_cc() local
120 now = MXC_TMR_GetCount(regs); in set_cc()
121 MXC_TMR_ClearFlags(regs); in set_cc()
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| /Zephyr-latest/drivers/sensor/bosch/bma4xx/ |
| D | bma4xx_emul.c | 29 uint8_t regs[BMA4XX_NUM_REGS]; member
41 memcpy(data->regs + reg_addr, val, count); in bma4xx_emul_set_reg()
49 memcpy(val, data->regs + reg_addr, count); in bma4xx_emul_get_reg()
57 *int1_io_ctrl = data->regs[BMA4XX_REG_INT1_IO_CTRL]; in bma4xx_emul_get_interrupt_config()
58 *latched_mode = data->regs[BMA4XX_REG_INT_LATCH]; in bma4xx_emul_get_interrupt_config()
59 return data->regs[BMA4XX_REG_INT_MAP_DATA]; in bma4xx_emul_get_interrupt_config()
84 data->regs[reg] = val & GENMASK(1, 0); in bma4xx_emul_write_byte()
91 data->regs[reg] = val; in bma4xx_emul_write_byte()
100 data->regs[reg] = (val & BMA4XX_FIFO_ACC_EN) != 0; in bma4xx_emul_write_byte()
103 data->regs[reg] = val; in bma4xx_emul_write_byte()
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| /Zephyr-latest/drivers/rtc/ |
| D | rtc_pcf8523.c | 348 uint8_t regs[7]; in pcf8523_set_time() local
369 regs[0] = bin2bcd(timeptr->tm_sec) & PCF8523_SECONDS_MASK; in pcf8523_set_time()
370 regs[1] = bin2bcd(timeptr->tm_min) & PCF8523_MINUTES_MASK; in pcf8523_set_time()
371 regs[2] = bin2bcd(timeptr->tm_hour) & PCF8523_HOURS_24H_MASK; in pcf8523_set_time()
372 regs[3] = bin2bcd(timeptr->tm_mday) & PCF8523_DAYS_MASK; in pcf8523_set_time()
373 regs[4] = bin2bcd(timeptr->tm_wday) & PCF8523_WEEKDAYS_MASK; in pcf8523_set_time()
374 regs[5] = bin2bcd(timeptr->tm_mon + PCF8523_MONTHS_OFFSET) & PCF8523_MONTHS_MASK; in pcf8523_set_time()
375 regs[6] = bin2bcd(timeptr->tm_year - PCF8523_YEARS_OFFSET) & PCF8523_YEARS_MASK; in pcf8523_set_time()
378 err = pcf8523_write_regs(dev, PCF8523_SECONDS, ®s, sizeof(regs)); in pcf8523_set_time()
397 uint8_t regs[10]; in pcf8523_get_time() local
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| /Zephyr-latest/tests/drivers/regulator/voltage/src/ |
| D | main.c | 19 static const struct device *regs[] = { variable
46 for (size_t i = 0U; i < ARRAY_SIZE(regs); i++) { in ZTEST()
54 volt_cnt = regulator_count_voltages(regs[i]); in ZTEST()
58 regs[i]->name, volt_cnt, tols[i]); in ZTEST()
60 ret = regulator_enable(regs[i]); in ZTEST()
66 (void)regulator_list_voltage(regs[i], j, &volt_uv); in ZTEST()
68 if (!regulator_is_supported_voltage(regs[i], in ZTEST()
78 ret = regulator_set_voltage(regs[i], volt_uv, volt_uv); in ZTEST()
105 ret = regulator_disable(regs[i]); in ZTEST()
112 zassert_equal(ARRAY_SIZE(regs), ARRAY_SIZE(adc_chs)); in setup()
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_sam0.c | 80 UsbDevice *regs = ®S->DEVICE; in usb_sam0_ep_isr() local
81 UsbDeviceEndpoint *endpoint = ®s->DeviceEndpoint[ep]; in usb_sam0_ep_isr()
105 regs->DADD.reg = data->addr; in usb_sam0_ep_isr()
115 UsbDevice *regs = ®S->DEVICE; in usb_sam0_isr() local
116 uint32_t intflag = regs->INTFLAG.reg; in usb_sam0_isr()
117 uint32_t epint = regs->EPINTSMRY.reg; in usb_sam0_isr()
121 regs->INTFLAG.reg = intflag; in usb_sam0_isr()
124 UsbDeviceEndpoint *endpoint = ®s->DeviceEndpoint[0]; in usb_sam0_isr()
149 UsbDevice *regs = ®S->DEVICE; in usb_sam0_wait_syncbusy() local
151 while (regs->SYNCBUSY.reg != 0) { in usb_sam0_wait_syncbusy()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_rv32m1_intmux.c | 43 INTMUX_Type *regs; member
49 #define DEV_REGS(dev) (((const struct rv32m1_intmux_config *)(dev->config))->regs)
57 INTMUX_Type *regs = DEV_REGS(dev); in rv32m1_intmux_irq_enable() local
61 regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line); in rv32m1_intmux_irq_enable()
66 INTMUX_Type *regs = DEV_REGS(dev); in rv32m1_intmux_irq_disable() local
70 regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line); in rv32m1_intmux_irq_disable()
75 INTMUX_Type *regs = DEV_REGS(dev); in rv32m1_intmux_get_state() local
79 if (regs->CHANNEL[i].CHn_IER_31_0) { in rv32m1_intmux_get_state()
90 INTMUX_Type *regs = DEV_REGS(dev); in rv32m1_intmux_get_line_state() local
94 if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) { in rv32m1_intmux_get_line_state()
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| D | intc_cavs.c | 60 volatile struct cavs_registers * const regs = get_base_address(context); in cavs_ictl_isr() local
62 cavs_ictl_dispatch_child_isrs(regs->status_il, in cavs_ictl_isr()
71 volatile struct cavs_registers * const regs = get_base_address(context); in cavs_ictl_irq_enable() local
73 regs->enable_il = 1 << irq; in cavs_ictl_irq_enable()
81 volatile struct cavs_registers * const regs = get_base_address(context); in cavs_ictl_irq_disable() local
83 regs->disable_il = 1 << irq; in cavs_ictl_irq_disable()
90 volatile struct cavs_registers * const regs = get_base_address(context); in cavs_ictl_irq_get_state() local
96 return regs->disable_state_il != 0xFFFFFFFF; in cavs_ictl_irq_get_state()
104 volatile struct cavs_registers * const regs = get_base_address(context); in cavs_ictl_irq_get_line_state() local
106 if ((regs->disable_state_il & BIT(irq)) == 0) { in cavs_ictl_irq_get_line_state()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_mchp_xec.c | 68 struct adc_xec_regs *regs; member
112 struct adc_xec_regs *regs = devcfg->regs; in adc_context_start_sampling() local
119 regs->single_reg = ctx->sequence.channels; in adc_context_start_sampling()
120 regs->control_reg |= XEC_ADC_CTRL_START_SINGLE; in adc_context_start_sampling()
137 struct adc_xec_regs * const regs = cfg->regs; in adc_xec_channel_setup() local
153 areg = regs->vref_channel_reg; in adc_xec_channel_setup()
164 regs->vref_channel_reg = areg; in adc_xec_channel_setup()
167 areg = regs->sar_control_reg; in adc_xec_channel_setup()
172 regs->sar_control_reg = areg; in adc_xec_channel_setup()
206 struct adc_xec_regs * const regs = cfg->regs; in adc_xec_start_read() local
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