29 	uint8_t regs[BMA4XX_NUM_REGS];  member
41 	memcpy(data->regs + reg_addr, val, count);  in bma4xx_emul_set_reg()
49 	memcpy(val, data->regs + reg_addr, count);  in bma4xx_emul_get_reg()
57 	*int1_io_ctrl = data->regs[BMA4XX_REG_INT1_IO_CTRL];  in bma4xx_emul_get_interrupt_config()
58 	*latched_mode = data->regs[BMA4XX_REG_INT_LATCH];  in bma4xx_emul_get_interrupt_config()
59 	return data->regs[BMA4XX_REG_INT_MAP_DATA];  in bma4xx_emul_get_interrupt_config()
84 		data->regs[reg] = val & GENMASK(1, 0);  in bma4xx_emul_write_byte()
91 		data->regs[reg] = val;  in bma4xx_emul_write_byte()
100 		data->regs[reg] = (val & BMA4XX_FIFO_ACC_EN) != 0;  in bma4xx_emul_write_byte()
103 		data->regs[reg] = val;  in bma4xx_emul_write_byte()
110 		data->regs[reg] = (val & 1) == 1;  in bma4xx_emul_write_byte()
113 		data->regs[reg] = val;  in bma4xx_emul_write_byte()
120 		data->regs[reg] = val;  in bma4xx_emul_write_byte()
125 		data->regs[reg] = val;  in bma4xx_emul_write_byte()
132 		data->regs[reg] = (val & BMA4XX_BIT_ACC_EN) != 0;  in bma4xx_emul_write_byte()
136 			data->regs[BMA4XX_REG_FIFO_DATA] = 0;  in bma4xx_emul_write_byte()
137 			data->regs[BMA4XX_REG_FIFO_LENGTH_0] = 0;  in bma4xx_emul_write_byte()
138 			data->regs[BMA4XX_REG_FIFO_LENGTH_1] = 0;  in bma4xx_emul_write_byte()
152 	data->regs[BMA4XX_REG_CHIP_ID] = BMA4XX_CHIP_ID_BMA422;  in bma4xx_emul_init()
153 	data->regs[BMA4XX_REG_ACCEL_RANGE] = BMA4XX_RANGE_4G;  in bma4xx_emul_init()
204 	int64_t accel_range = (2 << data->regs[BMA4XX_REG_ACCEL_RANGE]);  in bma4xx_emul_set_accel_data()
215 	data->regs[reg] = FIELD_GET(GENMASK(3, 0), reg_val) << 4;  in bma4xx_emul_set_accel_data()
216 	data->regs[reg + 1] = FIELD_GET(GENMASK(11, 4), reg_val);  in bma4xx_emul_set_accel_data()
248 	data->regs[BMA4XX_REG_INT_STAT_1] |= BMA4XX_ACC_DRDY_INT;  in bma4xx_emul_backend_set_channel()
273 	switch (data->regs[BMA4XX_REG_ACCEL_RANGE]) {  in bma4xx_emul_backend_get_sample_range()