1 /*
2 * Copyright (c) 2024 Michael Hope
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/drivers/clock_control.h>
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/drivers/gpio/gpio_utils.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/irq.h>
12
13 #include <ch32fun.h>
14
15 #define DT_DRV_COMPAT wch_gpio
16
17 struct gpio_ch32v00x_config {
18 struct gpio_driver_config common;
19 GPIO_TypeDef *regs;
20 const struct device *clock_dev;
21 uint8_t clock_id;
22 };
23
24 struct gpio_ch32v00x_data {
25 struct gpio_driver_data common;
26 };
27
gpio_ch32v00x_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)28 static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
29 {
30 const struct gpio_ch32v00x_config *config = dev->config;
31 GPIO_TypeDef *regs = config->regs;
32 uint32_t cnf_mode;
33 uint32_t bshr = 0;
34
35 if ((flags & GPIO_OUTPUT) != 0) {
36 cnf_mode = 0x01;
37 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
38 bshr = 1 << pin;
39 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
40 bshr = 1 << (16 + pin);
41 }
42 } else if ((flags & GPIO_INPUT) != 0) {
43 if ((flags & GPIO_PULL_UP) != 0) {
44 cnf_mode = GPIO_CFGLR_IN_PUPD;
45 bshr = 1 << pin;
46 } else if ((flags & GPIO_PULL_DOWN) != 0) {
47 cnf_mode = GPIO_CFGLR_IN_PUPD;
48 bshr = 1 << (16 + pin);
49 } else {
50 cnf_mode = GPIO_CFGLR_IN_FLOAT;
51 }
52 } else {
53 cnf_mode = 0x00;
54 }
55
56 regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin));
57 regs->BSHR = bshr;
58
59 return 0;
60 }
61
gpio_ch32v00x_port_get_raw(const struct device * dev,uint32_t * value)62 static int gpio_ch32v00x_port_get_raw(const struct device *dev, uint32_t *value)
63 {
64 const struct gpio_ch32v00x_config *config = dev->config;
65
66 *value = config->regs->INDR;
67
68 return 0;
69 }
70
gpio_ch32v00x_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)71 static int gpio_ch32v00x_port_set_masked_raw(const struct device *dev, uint32_t mask,
72 uint32_t value)
73 {
74 const struct gpio_ch32v00x_config *config = dev->config;
75
76 config->regs->BSHR = ((~value & mask) << 16) | (value & mask);
77
78 return 0;
79 }
80
gpio_ch32v00x_port_set_bits_raw(const struct device * dev,uint32_t pins)81 static int gpio_ch32v00x_port_set_bits_raw(const struct device *dev, uint32_t pins)
82 {
83 const struct gpio_ch32v00x_config *config = dev->config;
84
85 config->regs->BSHR = pins;
86
87 return 0;
88 }
89
gpio_ch32v00x_port_clear_bits_raw(const struct device * dev,uint32_t pins)90 static int gpio_ch32v00x_port_clear_bits_raw(const struct device *dev, uint32_t pins)
91 {
92 const struct gpio_ch32v00x_config *config = dev->config;
93
94 config->regs->BCR = pins;
95
96 return 0;
97 }
98
gpio_ch32v00x_port_toggle_bits(const struct device * dev,uint32_t pins)99 static int gpio_ch32v00x_port_toggle_bits(const struct device *dev, uint32_t pins)
100 {
101 const struct gpio_ch32v00x_config *config = dev->config;
102 uint32_t changed = (config->regs->OUTDR ^ pins) & pins;
103
104 config->regs->BSHR = (changed & pins) | (~changed & pins) << 16;
105
106 return 0;
107 }
108
109 static DEVICE_API(gpio, gpio_ch32v00x_driver_api) = {
110 .pin_configure = gpio_ch32v00x_configure,
111 .port_get_raw = gpio_ch32v00x_port_get_raw,
112 .port_set_masked_raw = gpio_ch32v00x_port_set_masked_raw,
113 .port_set_bits_raw = gpio_ch32v00x_port_set_bits_raw,
114 .port_clear_bits_raw = gpio_ch32v00x_port_clear_bits_raw,
115 .port_toggle_bits = gpio_ch32v00x_port_toggle_bits,
116 };
117
gpio_ch32v00x_init(const struct device * dev)118 static int gpio_ch32v00x_init(const struct device *dev)
119 {
120 const struct gpio_ch32v00x_config *config = dev->config;
121
122 clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id);
123
124 return 0;
125 }
126
127 #define GPIO_CH32V00X_INIT(idx) \
128 static const struct gpio_ch32v00x_config gpio_ch32v00x_##idx##_config = { \
129 .common = \
130 { \
131 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
132 }, \
133 .regs = (GPIO_TypeDef *)DT_INST_REG_ADDR(idx), \
134 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
135 .clock_id = DT_INST_CLOCKS_CELL(idx, id), \
136 }; \
137 \
138 static struct gpio_ch32v00x_data gpio_ch32v00x_##idx##_data; \
139 \
140 DEVICE_DT_INST_DEFINE(idx, gpio_ch32v00x_init, NULL, &gpio_ch32v00x_##idx##_data, \
141 &gpio_ch32v00x_##idx##_config, PRE_KERNEL_1, \
142 CONFIG_GPIO_INIT_PRIORITY, &gpio_ch32v00x_driver_api);
143
144 DT_INST_FOREACH_STATUS_OKAY(GPIO_CH32V00X_INIT)
145
