75 	struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;  in soc_deep_sleep_non_wake_en()  local
77 	regs->GIRQ22.SRC = UINT32_MAX;  in soc_deep_sleep_non_wake_en()
78 	regs->GIRQ22.EN_SET = MCHP_ESPI_WK_CLK_GIRQ_BIT;  in soc_deep_sleep_non_wake_en()
85 	struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;  in soc_deep_sleep_non_wake_dis()  local
87 	regs->GIRQ22.EN_CLR = UINT32_MAX;  in soc_deep_sleep_non_wake_dis()
88 	regs->GIRQ22.SRC = UINT32_MAX;  in soc_deep_sleep_non_wake_dis()
97 	struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;  in soc_deep_sleep_wake_en()  local
100 	regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT;  in soc_deep_sleep_wake_en()
101 	regs->GIRQ21.EN_SET = MCHP_KEYSCAN_GIRQ_BIT;  in soc_deep_sleep_wake_en()
105 	regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_en()
106 	regs->GIRQ21.EN_SET = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_en()
114 	struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;  in soc_deep_sleep_wake_dis()  local
117 	regs->GIRQ21.EN_CLR = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_dis()
118 	regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_dis()
157 	struct ecs_regs *regs = ECS_XEC_REG_BASE;  in deep_sleep_save_ecs()  local
159 	ds_ctx.ecs[0] = regs->ETM_CTRL;  in deep_sleep_save_ecs()
160 	ds_ctx.ecs[1] = regs->DEBUG_CTRL;  in deep_sleep_save_ecs()
162 	regs->ETM_CTRL = 0;  in deep_sleep_save_ecs()
163 	regs->DEBUG_CTRL = 0x00;  in deep_sleep_save_ecs()
170 	struct uart_regs *regs = UART_0_XEC_REG_BASE;  in deep_sleep_save_uarts()  local
172 	ds_ctx.uart_info[0] = regs->ACTV;  in deep_sleep_save_uarts()
174 		while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
177 	regs->ACTV = 0;  in deep_sleep_save_uarts()
179 	regs = UART_1_XEC_REG_BASE;  in deep_sleep_save_uarts()
180 	ds_ctx.uart_info[1] = regs->ACTV;  in deep_sleep_save_uarts()
182 		while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
185 	regs->ACTV = 0;  in deep_sleep_save_uarts()
209 	struct ecs_regs *regs = ECS_XEC_REG_BASE;  in deep_sleep_restore_ecs()  local
211 	regs->ETM_CTRL = ds_ctx.ecs[0];  in deep_sleep_restore_ecs()
212 	regs->DEBUG_CTRL = ds_ctx.ecs[1];  in deep_sleep_restore_ecs()