68 	struct adc_xec_regs *regs;  member
112 	struct adc_xec_regs *regs = devcfg->regs;  in adc_context_start_sampling()  local
119 	regs->single_reg = ctx->sequence.channels;  in adc_context_start_sampling()
120 	regs->control_reg |= XEC_ADC_CTRL_START_SINGLE;  in adc_context_start_sampling()
137 	struct adc_xec_regs * const regs = cfg->regs;  in adc_xec_channel_setup()  local
153 	areg = regs->vref_channel_reg;  in adc_xec_channel_setup()
164 	regs->vref_channel_reg = areg;  in adc_xec_channel_setup()
167 	areg = regs->sar_control_reg;  in adc_xec_channel_setup()
172 	regs->sar_control_reg = areg;  in adc_xec_channel_setup()
206 	struct adc_xec_regs * const regs = cfg->regs;  in adc_xec_start_read()  local
226 	sar_ctrl = regs->sar_control_reg;  in adc_xec_start_read()
239 	regs->sar_control_reg = sar_ctrl;  in adc_xec_start_read()
280 	struct adc_xec_regs * const regs = cfg->regs;  in xec_adc_get_sample()  local
283 	uint32_t channels = regs->status_reg;  in xec_adc_get_sample()
298 		*data->buffer = (uint16_t)regs->channel_read_reg[idx];  in xec_adc_get_sample()
306 	regs->status_reg = ch_status;  in xec_adc_get_sample()
345 	struct adc_xec_regs * const regs = cfg->regs;  in adc_xec_single_isr()  local
350 	ctrl = regs->control_reg;  in adc_xec_single_isr()
353 	regs->control_reg = ctrl;  in adc_xec_single_isr()
374 	struct adc_xec_regs * const adc_regs = devcfg->regs;  in adc_xec_pm_action()
419 	struct adc_xec_regs * const regs = cfg->regs;  in adc_xec_init()  local
431 	regs->config_reg = XEC_ADC_CFG_CLK_VAL(DT_INST_PROP(0, clktime));  in adc_xec_init()
433 	regs->control_reg =  XEC_ADC_CTRL_ACTIVATE  in adc_xec_init()
457 	.regs = (struct adc_xec_regs *)(DT_INST_REG_ADDR(0)),