1 /*
2 * Copyright (c) 2018 Foundries.io
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT openisa_rv32m1_intmux
8
9 /**
10 * @file
11 * @brief RV32M1 INTMUX (interrupt multiplexer) driver
12 *
13 * This driver provides support for level 2 interrupts on the RV32M1
14 * SoC using the INTMUX peripheral.
15 *
16 * Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral;
17 * INTMUX0 is wired to the RI5CY event unit interrupt table, while
18 * INTMUX1 is used with ZERO-RISCY.
19 *
20 * For this reason, only a single intmux device is declared here. The
21 * dtsi for each core needs to set up the intmux device and any
22 * associated IRQ numbers to work with this driver.
23 */
24
25 #include <zephyr/kernel.h>
26 #include <zephyr/devicetree/interrupt_controller.h>
27 #include <zephyr/drivers/clock_control.h>
28 #include <zephyr/init.h>
29 #include <zephyr/irq.h>
30 #include <zephyr/irq_nextlevel.h>
31 #include <zephyr/sw_isr_table.h>
32 #include <soc.h>
33 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
34
35 /*
36 * CHn_VEC registers are offset by a value that is convenient if
37 * you're dealing with a Cortex-M NVIC vector table; we're not, so it
38 * needs to be subtracted out to get a useful value.
39 */
40 #define VECN_OFFSET 48U
41
42 struct rv32m1_intmux_config {
43 INTMUX_Type *regs;
44 const struct device *clock_dev;
45 clock_control_subsys_t clock_subsys;
46 struct _isr_table_entry *isr_base;
47 };
48
49 #define DEV_REGS(dev) (((const struct rv32m1_intmux_config *)(dev->config))->regs)
50
51 /*
52 * <irq_nextlevel.h> API
53 */
54
rv32m1_intmux_irq_enable(const struct device * dev,uint32_t irq)55 static void rv32m1_intmux_irq_enable(const struct device *dev, uint32_t irq)
56 {
57 INTMUX_Type *regs = DEV_REGS(dev);
58 uint32_t channel = rv32m1_intmux_channel(irq);
59 uint32_t line = rv32m1_intmux_line(irq);
60
61 regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line);
62 }
63
rv32m1_intmux_irq_disable(const struct device * dev,uint32_t irq)64 static void rv32m1_intmux_irq_disable(const struct device *dev, uint32_t irq)
65 {
66 INTMUX_Type *regs = DEV_REGS(dev);
67 uint32_t channel = rv32m1_intmux_channel(irq);
68 uint32_t line = rv32m1_intmux_line(irq);
69
70 regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line);
71 }
72
rv32m1_intmux_get_state(const struct device * dev)73 static uint32_t rv32m1_intmux_get_state(const struct device *dev)
74 {
75 INTMUX_Type *regs = DEV_REGS(dev);
76 size_t i;
77
78 for (i = 0; i < INTMUX_CHn_IER_31_0_COUNT; i++) {
79 if (regs->CHANNEL[i].CHn_IER_31_0) {
80 return 1;
81 }
82 }
83
84 return 0;
85 }
86
rv32m1_intmux_get_line_state(const struct device * dev,unsigned int irq)87 static int rv32m1_intmux_get_line_state(const struct device *dev,
88 unsigned int irq)
89 {
90 INTMUX_Type *regs = DEV_REGS(dev);
91 uint32_t channel = rv32m1_intmux_channel(irq);
92 uint32_t line = rv32m1_intmux_line(irq);
93
94 if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) {
95 return 1;
96 }
97
98 return 0;
99 }
100
101 /*
102 * IRQ handling.
103 */
104
105 #define ISR_ENTRY(channel, line) \
106 ((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line)
107
rv32m1_intmux_isr(const void * arg)108 static void rv32m1_intmux_isr(const void *arg)
109 {
110 const struct device *const dev = DEVICE_DT_INST_GET(0);
111 const struct rv32m1_intmux_config *config = dev->config;
112 INTMUX_Type *regs = DEV_REGS(dev);
113 uint32_t channel = POINTER_TO_UINT(arg);
114 uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2);
115 struct _isr_table_entry *isr_base = config->isr_base;
116 struct _isr_table_entry *entry;
117
118 /*
119 * Make sure the vector is valid, there is a note of page 1243~1244
120 * of chapter 36 INTMUX of RV32M1 RM,
121 * Note: Unlike the NVIC, the INTMUX does not latch pending source
122 * interrupts. This means that the INTMUX output channel ISRs must
123 * check for and handle a 0 value of the CHn_VEC register to
124 * account for spurious interrupts.
125 */
126 if (line < VECN_OFFSET) {
127 return;
128 }
129
130 entry = &isr_base[ISR_ENTRY(channel, (line - VECN_OFFSET))];
131 entry->isr(entry->arg);
132 }
133
134 /*
135 * Instance and initialization
136 */
137
138 static const struct irq_next_level_api rv32m1_intmux_apis = {
139 .intr_enable = rv32m1_intmux_irq_enable,
140 .intr_disable = rv32m1_intmux_irq_disable,
141 .intr_get_state = rv32m1_intmux_get_state,
142 .intr_get_line_state = rv32m1_intmux_get_line_state,
143 };
144
145 static const struct rv32m1_intmux_config rv32m1_intmux_cfg = {
146 .regs = (INTMUX_Type *)DT_INST_REG_ADDR(0),
147 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
148 .clock_subsys = UINT_TO_POINTER(DT_INST_CLOCKS_CELL(0, name)),
149 .isr_base = &_sw_isr_table[CONFIG_2ND_LVL_ISR_TBL_OFFSET],
150 };
151
rv32m1_intmux_init(const struct device * dev)152 static int rv32m1_intmux_init(const struct device *dev)
153 {
154 const struct rv32m1_intmux_config *config = dev->config;
155 INTMUX_Type *regs = DEV_REGS(dev);
156 size_t i;
157
158 if (!device_is_ready(config->clock_dev)) {
159 return -ENODEV;
160 }
161
162 /* Enable INTMUX clock. */
163 clock_control_on(config->clock_dev, config->clock_subsys);
164
165 /*
166 * Reset all channels, not just the ones we're configured to
167 * support. We don't want to continue to take level 2 IRQs
168 * enabled by bootloaders, for example.
169 */
170 for (i = 0; i < INTMUX_CHn_CSR_COUNT; i++) {
171 regs->CHANNEL[i].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
172 }
173
174 /* Connect and enable level 1 (channel) interrupts. */
175 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_0
176 IRQ_CONNECT(INTMUX_CH0_IRQ, 0, rv32m1_intmux_isr,
177 UINT_TO_POINTER(0), 0);
178 irq_enable(INTMUX_CH0_IRQ);
179 #endif
180 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_1
181 IRQ_CONNECT(INTMUX_CH1_IRQ, 0, rv32m1_intmux_isr,
182 UINT_TO_POINTER(1), 0);
183 irq_enable(INTMUX_CH1_IRQ);
184 #endif
185 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_2
186 IRQ_CONNECT(INTMUX_CH2_IRQ, 0, rv32m1_intmux_isr,
187 UINT_TO_POINTER(2), 0);
188 irq_enable(INTMUX_CH2_IRQ);
189 #endif
190 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_3
191 IRQ_CONNECT(INTMUX_CH3_IRQ, 0, rv32m1_intmux_isr,
192 UINT_TO_POINTER(3), 0);
193 irq_enable(INTMUX_CH3_IRQ);
194 #endif
195 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_4
196 IRQ_CONNECT(INTMUX_CH4_IRQ, 0, rv32m1_intmux_isr,
197 UINT_TO_POINTER(4), 0);
198 irq_enable(INTMUX_CH4_IRQ);
199 #endif
200 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_5
201 IRQ_CONNECT(INTMUX_CH5_IRQ, 0, rv32m1_intmux_isr,
202 UINT_TO_POINTER(5), 0);
203 irq_enable(INTMUX_CH5_IRQ);
204 #endif
205 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_6
206 IRQ_CONNECT(INTMUX_CH6_IRQ, 0, rv32m1_intmux_isr,
207 UINT_TO_POINTER(6), 0);
208 irq_enable(INTMUX_CH6_IRQ);
209 #endif
210 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_7
211 IRQ_CONNECT(INTMUX_CH7_IRQ, 0, rv32m1_intmux_isr,
212 UINT_TO_POINTER(7), 0);
213 irq_enable(INTMUX_CH7_IRQ);
214 #endif
215
216 return 0;
217 }
218
219 DEVICE_DT_INST_DEFINE(0, &rv32m1_intmux_init, NULL, NULL,
220 &rv32m1_intmux_cfg, PRE_KERNEL_1,
221 CONFIG_RV32M1_INTMUX_INIT_PRIORITY, &rv32m1_intmux_apis);
222
223 #define INTC_CHILD_IRQ_ENTRY_DEF(node_id) \
224 IRQ_PARENT_ENTRY_DEFINE(CONCAT(DT_DRV_COMPAT, _child_, DT_NODE_CHILD_IDX(node_id)), NULL, \
225 DT_IRQN(node_id), INTC_CHILD_ISR_TBL_OFFSET(node_id), \
226 DT_INTC_GET_AGGREGATOR_LEVEL(node_id));
227
228 DT_INST_FOREACH_CHILD_STATUS_OKAY(0, INTC_CHILD_IRQ_ENTRY_DEF);
229
