1 /*
2 * Copyright (c) 2020 Vossloh Cogifer
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32h7_flash_controller
8
9 #include <zephyr/sys/util.h>
10 #include <zephyr/kernel.h>
11 #include <zephyr/device.h>
12 #include <string.h>
13 #include <zephyr/drivers/flash.h>
14 #include <zephyr/init.h>
15 #include <zephyr/sys/barrier.h>
16 #include <soc.h>
17 #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
18 #include <stm32h7rsxx_ll_bus.h>
19 #include <stm32h7rsxx_ll_utils.h>
20 #else
21 #include <stm32h7xx_ll_bus.h>
22 #include <stm32h7xx_ll_utils.h>
23 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
24
25 #include "flash_stm32.h"
26 #include "stm32_hsem.h"
27
28 #define LOG_DOMAIN flash_stm32h7
29 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
30 #include <zephyr/logging/log.h>
31 LOG_MODULE_REGISTER(LOG_DOMAIN);
32
33 /* Let's wait for double the max erase time to be sure that the operation is
34 * completed.
35 */
36 #define STM32H7_FLASH_TIMEOUT (2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
37
38 #define STM32H7_M4_FLASH_SIZE DT_PROP_OR(DT_INST(0, st_stm32_nv_flash), bank2_flash_size, 0)
39 #ifdef CONFIG_CPU_CORTEX_M4
40 #if STM32H7_M4_FLASH_SIZE == 0
41 #error Flash driver on M4 requires the DT property bank2-flash-size
42 #else
43 #define REAL_FLASH_SIZE_KB (KB(STM32H7_M4_FLASH_SIZE * 2))
44 #endif
45 #else
46 #define REAL_FLASH_SIZE_KB KB(LL_GetFlashSize())
47 #endif
48 #define SECTOR_PER_BANK ((REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE) / 2)
49 #if defined(DUAL_BANK)
50 #define STM32H7_SERIES_MAX_FLASH_KB KB(2048)
51 #define BANK2_OFFSET (STM32H7_SERIES_MAX_FLASH_KB / 2)
52 /* When flash is dual bank and flash size is smaller than Max flash size of
53 * the serie, there is a discontinuty between bank1 and bank2.
54 */
55 #define DISCONTINUOUS_BANKS (REAL_FLASH_SIZE_KB < STM32H7_SERIES_MAX_FLASH_KB)
56 #endif
57
58 struct flash_stm32_sector_t {
59 int sector_index;
60 int bank;
61 volatile uint32_t *cr;
62 volatile uint32_t *sr;
63 };
64
write_optb(const struct device * dev,uint32_t mask,uint32_t value)65 static __unused int write_optb(const struct device *dev, uint32_t mask,
66 uint32_t value)
67 {
68 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
69 int rc;
70
71 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
72 LOG_ERR("Option bytes locked");
73 return -EIO;
74 }
75
76 if ((regs->OPTCR & mask) == value) {
77 /* Done already */
78 return 0;
79 }
80
81 rc = flash_stm32_wait_flash_idle(dev);
82 if (rc < 0) {
83 LOG_ERR("Err flash no idle");
84 return rc;
85 }
86
87 regs->OPTCR = (regs->OPTCR & ~mask) | value;
88 #ifdef CONFIG_SOC_SERIES_STM32H7RSX
89 regs->OPTCR |= FLASH_OPTCR_PG_OPT;
90 #else
91 regs->OPTCR |= FLASH_OPTCR_OPTSTART;
92 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
93 /* Make sure previous write is completed. */
94 barrier_dsync_fence_full();
95
96 rc = flash_stm32_wait_flash_idle(dev);
97 if (rc < 0) {
98 LOG_ERR("Err flash no idle");
99 return rc;
100 }
101
102 return 0;
103 }
104
105 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
flash_stm32_get_rdp_level(const struct device * dev)106 uint8_t flash_stm32_get_rdp_level(const struct device *dev)
107 {
108 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
109
110 return (regs->OPTSR_CUR & FLASH_OPTSR_RDP_Msk) >> FLASH_OPTSR_RDP_Pos;
111 }
112
flash_stm32_set_rdp_level(const struct device * dev,uint8_t level)113 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
114 {
115 write_optb(dev, FLASH_OPTSR_RDP_Msk,
116 (uint32_t)level << FLASH_OPTSR_RDP_Pos);
117 }
118 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
119
flash_stm32_option_bytes_lock(const struct device * dev,bool enable)120 int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
121 {
122 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
123
124 if (enable) {
125 regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
126 } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
127 #ifdef CONFIG_SOC_SERIES_STM32H7RSX
128 regs->OPTKEYR = FLASH_OPTKEY1;
129 regs->OPTKEYR = FLASH_OPTKEY2;
130 #else
131 regs->OPTKEYR = FLASH_OPT_KEY1;
132 regs->OPTKEYR = FLASH_OPT_KEY2;
133 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
134 }
135
136 if (enable) {
137 LOG_DBG("Option bytes locked");
138 } else {
139 LOG_DBG("Option bytes unlocked");
140 }
141
142 return 0;
143 }
144
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)145 bool flash_stm32_valid_range(const struct device *dev, off_t offset, uint32_t len, bool write)
146 {
147 #if defined(DUAL_BANK)
148 if (DISCONTINUOUS_BANKS) {
149 /*
150 * In case of bank1/2 discontinuity, the range should not
151 * start before bank2 and end beyond bank1 at the same time.
152 * Locations beyond bank2 are caught by flash_stm32_range_exists
153 */
154 if ((offset < BANK2_OFFSET) && (offset + len > REAL_FLASH_SIZE_KB / 2)) {
155 LOG_ERR("Range ovelaps flash bank discontinuity");
156 return false;
157 }
158 }
159 #endif
160
161 if (write) {
162 if ((offset % (FLASH_NB_32BITWORD_IN_FLASHWORD * 4)) != 0) {
163 LOG_ERR("Write offset not aligned on flashword length. "
164 "Offset: 0x%lx, flashword length: %d",
165 (unsigned long)offset, FLASH_NB_32BITWORD_IN_FLASHWORD * 4);
166 return false;
167 }
168 }
169 return flash_stm32_range_exists(dev, offset, len);
170 }
171
flash_stm32_check_status(const struct device * dev)172 static int flash_stm32_check_status(const struct device *dev)
173 {
174 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
175 /* The hardware corrects single ECC errors and detects double
176 * ECC errors. Corrected data is returned for single ECC
177 * errors, so in this case we just log a warning.
178 */
179 #ifdef DUAL_BANK
180 uint32_t const error_bank2 = (FLASH_FLAG_ALL_ERRORS_BANK2 & ~FLASH_FLAG_SNECCERR_BANK2);
181 #endif
182 uint32_t sr;
183
184 #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
185 uint32_t const error_bank =
186 (FLASH_FLAG_ECC_ERRORS & ~FLASH_FLAG_SNECCERR & ~FLASH_FLAG_DBECCERR);
187
188 /* Read the Interrupt status flags. */
189 sr = regs->ISR;
190 if (sr & (FLASH_FLAG_SNECCERR)) {
191 uint32_t word = regs->ECCSFADDR & FLASH_ECCSFADDR_SEC_FADD;
192
193 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
194 word * 4 * FLASH_NB_32BITWORD_IN_FLASHWORD);
195 }
196
197 if (sr & (FLASH_FLAG_DBECCERR)) {
198 uint32_t word = regs->ECCDFADDR & FLASH_ECCDFADDR_DED_FADD;
199
200 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
201 word * 4 * FLASH_NB_32BITWORD_IN_FLASHWORD);
202 }
203
204 /* Clear the ECC flags (including FA) */
205 regs->ICR = FLASH_FLAG_ECC_ERRORS;
206 if (sr & error_bank) {
207 #else
208 uint32_t const error_bank1 = (FLASH_FLAG_ALL_ERRORS_BANK1 & ~FLASH_FLAG_SNECCERR_BANK1);
209
210 /* Read the status flags. */
211 sr = regs->SR1;
212 if (sr & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1)) {
213 uint32_t word = regs->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR;
214
215 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
216 word * 4 * FLASH_NB_32BITWORD_IN_FLASHWORD);
217 }
218 /* Clear the flags (including FA1R) */
219 regs->CCR1 = FLASH_FLAG_ALL_BANK1;
220
221 if (sr & error_bank1) {
222 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
223 LOG_ERR("Status Bank%d: 0x%08x", 1, sr);
224 return -EIO;
225 }
226
227 #ifdef DUAL_BANK
228 sr = regs->SR2;
229 if (sr & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1)) {
230 uint32_t word = regs->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR;
231
232 LOG_WRN("Bank%d ECC error at 0x%08x", 2,
233 word * 4 * FLASH_NB_32BITWORD_IN_FLASHWORD);
234 }
235 regs->CCR2 = FLASH_FLAG_ALL_BANK2;
236 if (sr & error_bank2) {
237 /* Sometimes the STRBERR is seen when writing to flash
238 * from M4 (upper 128KiB) with code running from lower
239 * 896KiB. Don't know why it happens, but technical
240 * reference manual (section 4.7.4) says application can
241 * ignore this error and continue with normal write. So
242 * check and return here if the error is STRBERR and clear
243 * the error by setting CCR2 bit.
244 */
245 if (sr & FLASH_FLAG_STRBERR_BANK2) {
246 regs->CCR2 |= FLASH_FLAG_STRBERR_BANK2;
247 return 0;
248 }
249 LOG_ERR("Status Bank%d: 0x%08x", 2, sr);
250 return -EIO;
251 }
252 #endif
253
254 return 0;
255 }
256
257 int flash_stm32_wait_flash_idle(const struct device *dev)
258 {
259 int64_t timeout_time = k_uptime_get() + STM32H7_FLASH_TIMEOUT;
260 int rc;
261
262 rc = flash_stm32_check_status(dev);
263 if (rc < 0) {
264 return -EIO;
265 }
266 #ifdef DUAL_BANK
267 while ((FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW) ||
268 (FLASH_STM32_REGS(dev)->SR2 & FLASH_SR_QW))
269 #else
270 while (FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW)
271 #endif
272 {
273 if (k_uptime_get() > timeout_time) {
274 LOG_ERR("Timeout! val: %d", STM32H7_FLASH_TIMEOUT);
275 return -EIO;
276 }
277 }
278
279 return 0;
280 }
281
282 static struct flash_stm32_sector_t get_sector(const struct device *dev, off_t offset)
283 {
284 struct flash_stm32_sector_t sector;
285 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
286
287 #ifdef DUAL_BANK
288 off_t temp_offset = offset + (CONFIG_FLASH_BASE_ADDRESS & 0xffffff);
289
290 bool bank_swap;
291 /* Check whether bank1/2 are swapped */
292 bank_swap = (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == FLASH_OPTCR_SWAP_BANK);
293 sector.sector_index = offset / FLASH_SECTOR_SIZE;
294 if ((temp_offset < (REAL_FLASH_SIZE_KB / 2)) && !bank_swap) {
295 sector.bank = 1;
296 sector.cr = ®s->CR1;
297 sector.sr = ®s->SR1;
298 } else if ((temp_offset >= BANK2_OFFSET) && bank_swap) {
299 sector.sector_index -= BANK2_OFFSET / FLASH_SECTOR_SIZE;
300 sector.bank = 1;
301 sector.cr = ®s->CR2;
302 sector.sr = ®s->SR2;
303 } else if ((temp_offset < (REAL_FLASH_SIZE_KB / 2)) && bank_swap) {
304 sector.bank = 2;
305 sector.cr = ®s->CR1;
306 sector.sr = ®s->SR1;
307 } else if ((temp_offset >= BANK2_OFFSET) && !bank_swap) {
308 sector.sector_index -= BANK2_OFFSET / FLASH_SECTOR_SIZE;
309 sector.bank = 2;
310 sector.cr = ®s->CR2;
311 sector.sr = ®s->SR2;
312 } else {
313 sector.sector_index = 0;
314 sector.bank = 0;
315 sector.cr = NULL;
316 sector.sr = NULL;
317 }
318 #else
319 if (offset < REAL_FLASH_SIZE_KB) {
320 sector.sector_index = offset / FLASH_SECTOR_SIZE;
321 sector.bank = 1;
322 sector.cr = ®s->CR1;
323 sector.sr = ®s->SR1;
324 } else {
325 sector.sector_index = 0;
326 sector.bank = 0;
327 sector.cr = NULL;
328 sector.sr = NULL;
329 }
330 #endif
331
332 return sector;
333 }
334
335 static int erase_sector(const struct device *dev, int offset)
336 {
337 int rc;
338 struct flash_stm32_sector_t sector = get_sector(dev, offset);
339
340 if (sector.bank == 0) {
341
342 LOG_ERR("Offset %ld does not exist", (long)offset);
343 return -EINVAL;
344 }
345
346 /* if the control register is locked, do not fail silently */
347 if (*(sector.cr) & FLASH_CR_LOCK) {
348 return -EIO;
349 }
350
351 rc = flash_stm32_wait_flash_idle(dev);
352 if (rc < 0) {
353 return rc;
354 }
355
356 *(sector.cr) &= ~FLASH_CR_SNB;
357 *(sector.cr) |= (FLASH_CR_SER | ((sector.sector_index << FLASH_CR_SNB_Pos) & FLASH_CR_SNB));
358 *(sector.cr) |= FLASH_CR_START;
359 /* flush the register write */
360 barrier_dsync_fence_full();
361
362 rc = flash_stm32_wait_flash_idle(dev);
363 *(sector.cr) &= ~(FLASH_CR_SER | FLASH_CR_SNB);
364
365 return rc;
366 }
367
368 int flash_stm32_block_erase_loop(const struct device *dev, unsigned int offset, unsigned int len)
369 {
370 unsigned int address = offset;
371 int rc = 0;
372
373 for (; address <= offset + len - 1; address += FLASH_SECTOR_SIZE) {
374 rc = erase_sector(dev, address);
375 if (rc < 0) {
376 break;
377 }
378 }
379 return rc;
380 }
381
382 static int wait_write_queue(const struct flash_stm32_sector_t *sector)
383 {
384 int64_t timeout_time = k_uptime_get() + 100;
385
386 while (*(sector->sr) & FLASH_SR_QW) {
387 if (k_uptime_get() > timeout_time) {
388 LOG_ERR("Timeout! val: %d", 100);
389 return -EIO;
390 }
391 }
392
393 return 0;
394 }
395
396 static int write_ndwords(const struct device *dev, off_t offset, const uint64_t *data, uint8_t n)
397 {
398 volatile uint64_t *flash = (uint64_t *)(offset + FLASH_STM32_BASE_ADDRESS);
399 int rc;
400 int i;
401 struct flash_stm32_sector_t sector = get_sector(dev, offset);
402
403 if (sector.bank == 0) {
404 LOG_ERR("Offset %ld does not exist", (long)offset);
405 return -EINVAL;
406 }
407
408 /* if the control register is locked, do not fail silently */
409 if (*(sector.cr) & FLASH_CR_LOCK) {
410 return -EIO;
411 }
412
413 /* Check that no Flash main memory operation is ongoing */
414 rc = flash_stm32_wait_flash_idle(dev);
415 if (rc < 0) {
416 return rc;
417 }
418
419 /* Check if 256 bits location is erased */
420 for (i = 0; i < n; ++i) {
421 if (flash[i] != 0xFFFFFFFFFFFFFFFFUL) {
422 return -EIO;
423 }
424 }
425
426 /* Set the PG bit */
427 *(sector.cr) |= FLASH_CR_PG;
428
429 /* Flush the register write */
430 barrier_dsync_fence_full();
431
432 /* Perform the data write operation at the desired memory address */
433 for (i = 0; i < n; ++i) {
434 /* Source dword may be unaligned, so take extra care when dereferencing it */
435 flash[i] = UNALIGNED_GET(data + i);
436
437 /* Flush the data write */
438 barrier_dsync_fence_full();
439
440 wait_write_queue(§or);
441 }
442
443 /* Wait until the BSY bit is cleared */
444 rc = flash_stm32_wait_flash_idle(dev);
445
446 /* Clear the PG bit */
447 *(sector.cr) &= (~FLASH_CR_PG);
448
449 return rc;
450 }
451
452 int flash_stm32_write_range(const struct device *dev, unsigned int offset, const void *data,
453 unsigned int len)
454 {
455 int rc = 0;
456 int i, j;
457 const uint8_t ndwords = FLASH_NB_32BITWORD_IN_FLASHWORD / 2;
458 const uint8_t nbytes = FLASH_NB_32BITWORD_IN_FLASHWORD * 4;
459 uint8_t unaligned_datas[nbytes];
460
461 for (i = 0; i < len && i + nbytes <= len; i += nbytes, offset += nbytes) {
462 rc = write_ndwords(dev, offset, (const uint64_t *)data + (i >> 3), ndwords);
463 if (rc < 0) {
464 return rc;
465 }
466 }
467
468 /* Handle the remaining bytes if length is not aligned on
469 * FLASH_NB_32BITWORD_IN_FLASHWORD
470 */
471 if (i < len) {
472 memset(unaligned_datas, 0xff, sizeof(unaligned_datas));
473 for (j = 0; j < len - i; ++j) {
474 unaligned_datas[j] = ((uint8_t *)data)[i + j];
475 }
476 rc = write_ndwords(dev, offset, (const uint64_t *)unaligned_datas, ndwords);
477 if (rc < 0) {
478 return rc;
479 }
480 }
481
482 return rc;
483 }
484
485 static int flash_stm32h7_write_protection(const struct device *dev, bool enable)
486 {
487 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
488
489 int rc = 0;
490
491 if (enable) {
492 rc = flash_stm32_wait_flash_idle(dev);
493 if (rc) {
494 return rc;
495 }
496 }
497
498 /* Bank 1 */
499 if (enable) {
500 regs->CR1 |= FLASH_CR_LOCK;
501 } else {
502 if (regs->CR1 & FLASH_CR_LOCK) {
503 regs->KEYR1 = FLASH_KEY1;
504 regs->KEYR1 = FLASH_KEY2;
505 }
506 }
507 #ifdef DUAL_BANK
508 /* Bank 2 */
509 if (enable) {
510 regs->CR2 |= FLASH_CR_LOCK;
511 } else {
512 if (regs->CR2 & FLASH_CR_LOCK) {
513 regs->KEYR2 = FLASH_KEY1;
514 regs->KEYR2 = FLASH_KEY2;
515 }
516 }
517 #endif
518
519 if (enable) {
520 LOG_DBG("Enable write protection");
521 } else {
522 LOG_DBG("Disable write protection");
523 }
524
525 return rc;
526 }
527
528 #ifdef CONFIG_CPU_CORTEX_M7
529 static void flash_stm32h7_flush_caches(const struct device *dev, off_t offset, size_t len)
530 {
531 ARG_UNUSED(dev);
532
533 if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
534 return; /* Cache not enabled */
535 }
536
537 SCB_InvalidateDCache_by_Addr((uint32_t *)(FLASH_STM32_BASE_ADDRESS + offset), len);
538 }
539 #endif /* CONFIG_CPU_CORTEX_M7 */
540
541 static int flash_stm32h7_erase(const struct device *dev, off_t offset, size_t len)
542 {
543 int rc, rc2;
544
545 #ifdef CONFIG_CPU_CORTEX_M7
546 /* Flush whole sectors */
547 off_t flush_offset = ROUND_DOWN(offset, FLASH_SECTOR_SIZE);
548 size_t flush_len = ROUND_UP(offset + len - 1, FLASH_SECTOR_SIZE) - flush_offset;
549 #endif /* CONFIG_CPU_CORTEX_M7 */
550
551 if (!flash_stm32_valid_range(dev, offset, len, true)) {
552 LOG_ERR("Erase range invalid. Offset: %ld, len: %zu", (long)offset, len);
553 return -EINVAL;
554 }
555
556 if (!len) {
557 return 0;
558 }
559
560 flash_stm32_sem_take(dev);
561
562 LOG_DBG("Erase offset: %ld, len: %zu", (long)offset, len);
563
564 rc = flash_stm32h7_write_protection(dev, false);
565 if (rc) {
566 goto done;
567 }
568
569 rc = flash_stm32_block_erase_loop(dev, offset, len);
570
571 #ifdef CONFIG_CPU_CORTEX_M7
572 /* Flush cache on all sectors affected by the erase */
573 flash_stm32h7_flush_caches(dev, flush_offset, flush_len);
574 #elif CONFIG_CPU_CORTEX_M4
575 if (LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ART) && LL_ART_IsEnabled()) {
576 LOG_ERR("Cortex M4: ART enabled not supported by flash driver");
577 }
578 #endif /* CONFIG_CPU_CORTEX_M7 */
579 done:
580 rc2 = flash_stm32h7_write_protection(dev, true);
581
582 if (!rc) {
583 rc = rc2;
584 }
585
586 flash_stm32_sem_give(dev);
587
588 return rc;
589 }
590
591 static int flash_stm32h7_write(const struct device *dev, off_t offset, const void *data, size_t len)
592 {
593 int rc;
594
595 if (!flash_stm32_valid_range(dev, offset, len, true)) {
596 LOG_ERR("Write range invalid. Offset: %ld, len: %zu", (long)offset, len);
597 return -EINVAL;
598 }
599
600 if (!len) {
601 return 0;
602 }
603
604 flash_stm32_sem_take(dev);
605
606 LOG_DBG("Write offset: %ld, len: %zu", (long)offset, len);
607
608 rc = flash_stm32h7_write_protection(dev, false);
609 if (!rc) {
610 rc = flash_stm32_write_range(dev, offset, data, len);
611 }
612
613 int rc2 = flash_stm32h7_write_protection(dev, true);
614
615 if (!rc) {
616 rc = rc2;
617 }
618
619 flash_stm32_sem_give(dev);
620
621 return rc;
622 }
623
624 static int flash_stm32h7_read(const struct device *dev, off_t offset, void *data, size_t len)
625 {
626 if (!flash_stm32_valid_range(dev, offset, len, false)) {
627 LOG_ERR("Read range invalid. Offset: %ld, len: %zu", (long)offset, len);
628 return -EINVAL;
629 }
630
631 if (!len) {
632 return 0;
633 }
634
635 LOG_DBG("Read offset: %ld, len: %zu", (long)offset, len);
636
637 /* During the read we mask bus errors and only allow NMI.
638 *
639 * If the flash has a double ECC error then there is normally
640 * a bus fault, but we want to return an error code instead.
641 */
642 unsigned int irq_lock_key = irq_lock();
643
644 __set_FAULTMASK(1);
645 SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
646 barrier_dsync_fence_full();
647 barrier_isync_fence_full();
648
649 memcpy(data, (uint8_t *)FLASH_STM32_BASE_ADDRESS + offset, len);
650
651 __set_FAULTMASK(0);
652 SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
653 barrier_dsync_fence_full();
654 barrier_isync_fence_full();
655 irq_unlock(irq_lock_key);
656
657 return flash_stm32_check_status(dev);
658 }
659
660 static const struct flash_parameters flash_stm32h7_parameters = {
661 .write_block_size = FLASH_STM32_WRITE_BLOCK_SIZE,
662 .erase_value = 0xff,
663 };
664
665 static const struct flash_parameters *flash_stm32h7_get_parameters(const struct device *dev)
666 {
667 ARG_UNUSED(dev);
668
669 return &flash_stm32h7_parameters;
670 }
671
672 void flash_stm32_page_layout(const struct device *dev, const struct flash_pages_layout **layout,
673 size_t *layout_size)
674 {
675 ARG_UNUSED(dev);
676
677 #if defined(DUAL_BANK)
678 static struct flash_pages_layout stm32h7_flash_layout[3];
679
680 if (DISCONTINUOUS_BANKS) {
681 if (stm32h7_flash_layout[0].pages_count == 0) {
682 /* Bank1 */
683 stm32h7_flash_layout[0].pages_count = SECTOR_PER_BANK;
684 stm32h7_flash_layout[0].pages_size = FLASH_SECTOR_SIZE;
685 /*
686 * Dummy page corresponding to discontinuity
687 * between bank1/2
688 */
689 stm32h7_flash_layout[1].pages_count = 1;
690 stm32h7_flash_layout[1].pages_size =
691 BANK2_OFFSET - (SECTOR_PER_BANK * FLASH_SECTOR_SIZE);
692 /* Bank2 */
693 stm32h7_flash_layout[2].pages_count = SECTOR_PER_BANK;
694 stm32h7_flash_layout[2].pages_size = FLASH_SECTOR_SIZE;
695 }
696 *layout_size = ARRAY_SIZE(stm32h7_flash_layout);
697 } else {
698 if (stm32h7_flash_layout[0].pages_count == 0) {
699 stm32h7_flash_layout[0].pages_count =
700 REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE;
701 stm32h7_flash_layout[0].pages_size = FLASH_SECTOR_SIZE;
702 }
703 *layout_size = 1;
704 }
705 #else
706 static struct flash_pages_layout stm32h7_flash_layout[1];
707
708 if (stm32h7_flash_layout[0].pages_count == 0) {
709 stm32h7_flash_layout[0].pages_count = REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE;
710 stm32h7_flash_layout[0].pages_size = FLASH_SECTOR_SIZE;
711 }
712 *layout_size = ARRAY_SIZE(stm32h7_flash_layout);
713 #endif
714 *layout = stm32h7_flash_layout;
715 }
716
717 static struct flash_stm32_priv flash_data = {
718 .regs = (FLASH_TypeDef *)DT_INST_REG_ADDR(0),
719 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
720 .pclken = {.bus = DT_INST_CLOCKS_CELL(0, bus), .enr = DT_INST_CLOCKS_CELL(0, bits)},
721 #endif
722 };
723
724 static DEVICE_API(flash, flash_stm32h7_api) = {
725 .erase = flash_stm32h7_erase,
726 .write = flash_stm32h7_write,
727 .read = flash_stm32h7_read,
728 .get_parameters = flash_stm32h7_get_parameters,
729 #ifdef CONFIG_FLASH_PAGE_LAYOUT
730 .page_layout = flash_stm32_page_layout,
731 #endif
732 #ifdef CONFIG_FLASH_EX_OP_ENABLED
733 .ex_op = flash_stm32_ex_op,
734 #endif
735 };
736
737 static int stm32h7_flash_init(const struct device *dev)
738 {
739 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
740 /* Only stm32h7 dual core devices have the clocks property */
741 struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
742 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
743
744 if (!device_is_ready(clk)) {
745 LOG_ERR("clock control device not ready");
746 return -ENODEV;
747 }
748
749 /* enable clock : enable the RCC_AHB3ENR_FLASHEN bit */
750 if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {
751 LOG_ERR("Failed to enable clock");
752 return -EIO;
753 }
754 #endif
755 flash_stm32_sem_init(dev);
756
757 LOG_DBG("Flash initialized. BS: %zu", flash_stm32h7_parameters.write_block_size);
758
759 #if ((CONFIG_FLASH_LOG_LEVEL >= LOG_LEVEL_DBG) && CONFIG_FLASH_PAGE_LAYOUT)
760 const struct flash_pages_layout *layout;
761 size_t layout_size;
762
763 flash_stm32_page_layout(dev, &layout, &layout_size);
764 for (size_t i = 0; i < layout_size; i++) {
765 LOG_DBG("Block %zu: bs: %zu count: %zu", i, layout[i].pages_size,
766 layout[i].pages_count);
767 }
768 #endif
769
770 return flash_stm32h7_write_protection(dev, false);
771 }
772
773 DEVICE_DT_INST_DEFINE(0, stm32h7_flash_init, NULL, &flash_data, NULL, POST_KERNEL,
774 CONFIG_FLASH_INIT_PRIORITY, &flash_stm32h7_api);
775
