111 	ETH_GLOBAL_TypeDef *regs;  member
143 	dev_cfg->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&tx_dma_desc[0];  in eth_xmc4xxx_tx_dma_descriptors_init()
162 	dev_cfg->regs->OPERATION_MODE &= ~ETH_OPERATION_MODE_SR_Msk;  in eth_xmc4xxx_flush_rx()
168 	dev_cfg->regs->OPERATION_MODE |= ETH_OPERATION_MODE_SR_Msk;  in eth_xmc4xxx_flush_rx()
184 	dev_cfg->regs->OPERATION_MODE &= ~ETH_OPERATION_MODE_ST_Msk;  in eth_xmc4xxx_flush_tx()
203 	dev_cfg->regs->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk;  in eth_xmc4xxx_flush_tx()
212 static inline void eth_xmc4xxx_trigger_dma_tx(ETH_GLOBAL_TypeDef *regs)  in eth_xmc4xxx_trigger_dma_tx()  argument
214 	regs->STATUS = ETH_STATUS_TPS_Msk;  in eth_xmc4xxx_trigger_dma_tx()
215 	regs->TRANSMIT_POLL_DEMAND = 0;  in eth_xmc4xxx_trigger_dma_tx()
218 static inline void eth_xmc4xxx_trigger_dma_rx(ETH_GLOBAL_TypeDef *regs)  in eth_xmc4xxx_trigger_dma_rx()  argument
220 	regs->STATUS = ETH_STATUS_RU_Msk;  in eth_xmc4xxx_trigger_dma_rx()
221 	regs->RECEIVE_POLL_DEMAND = 0U;  in eth_xmc4xxx_trigger_dma_rx()
253 		eth_xmc4xxx_trigger_dma_tx(dev_cfg->regs);  in eth_xmc4xxx_send()
345 	eth_xmc4xxx_trigger_dma_tx(dev_cfg->regs);  in eth_xmc4xxx_send()
473 	eth_xmc4xxx_trigger_dma_rx(dev_cfg->regs);  in eth_xmc4xxx_rx_pkt()
563 	status = dev_cfg->regs->STATUS;  in eth_xmc4xxx_isr()
583 	dev_cfg->regs->STATUS = status & ETH_STATUS_CLEARABLE_BITS;  in eth_xmc4xxx_isr()
588 static inline void eth_xmc4xxx_enable_tx(ETH_GLOBAL_TypeDef *regs)  in eth_xmc4xxx_enable_tx()  argument
590 	regs->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk;  in eth_xmc4xxx_enable_tx()
591 	regs->MAC_CONFIGURATION |= ETH_MAC_CONFIGURATION_TE_Msk;  in eth_xmc4xxx_enable_tx()
594 static inline void eth_xmc4xxx_enable_rx(ETH_GLOBAL_TypeDef *regs)  in eth_xmc4xxx_enable_rx()  argument
596 	regs->OPERATION_MODE |= ETH_OPERATION_MODE_SR_Msk;  in eth_xmc4xxx_enable_rx()
597 	regs->MAC_CONFIGURATION |= ETH_MAC_CONFIGURATION_RE_Msk;  in eth_xmc4xxx_enable_rx()
600 static inline void eth_xmc4xxx_set_link(ETH_GLOBAL_TypeDef *regs, struct phy_link_state *state)  in eth_xmc4xxx_set_link()  argument
602 	uint32_t reg = regs->MAC_CONFIGURATION;  in eth_xmc4xxx_set_link()
615 	regs->MAC_CONFIGURATION = reg;  in eth_xmc4xxx_set_link()
630 		eth_xmc4xxx_set_link(dev_cfg->regs, state);  in phy_link_state_changed()
665 	dev_cfg->regs->INTERRUPT_ENABLE |= ETH_STATUS_ALL_EVENTS;  in eth_xmc4xxx_iface_init()
667 	eth_xmc4xxx_enable_tx(dev_cfg->regs);  in eth_xmc4xxx_iface_init()
668 	eth_xmc4xxx_enable_rx(dev_cfg->regs);  in eth_xmc4xxx_iface_init()
697 	dev_cfg->regs->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&rx_dma_desc[0];  in eth_xmc4xxx_rx_dma_descriptors_init()
732 	dev_cfg->regs->BUS_MODE |= ETH_BUS_MODE_SWR_Msk;  in eth_xmc4xxx_reset()
735 	if (!WAIT_FOR((dev_cfg->regs->BUS_MODE & ETH_BUS_MODE_SWR_Msk) == 0,  in eth_xmc4xxx_reset()
743 static inline void eth_xmc4xxx_set_mac_address(ETH_GLOBAL_TypeDef *regs, uint8_t *const addr)  in eth_xmc4xxx_set_mac_address()  argument
745 	regs->MAC_ADDRESS0_HIGH = addr[4] | (addr[5] << 8);  in eth_xmc4xxx_set_mac_address()
746 	regs->MAC_ADDRESS0_LOW = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);  in eth_xmc4xxx_set_mac_address()
749 static inline void eth_xmc4xxx_mask_unused_interrupts(ETH_GLOBAL_TypeDef *regs)  in eth_xmc4xxx_mask_unused_interrupts()  argument
752 	regs->MMC_TRANSMIT_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK;  in eth_xmc4xxx_mask_unused_interrupts()
753 	regs->MMC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK;  in eth_xmc4xxx_mask_unused_interrupts()
756 	regs->MMC_IPC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK;  in eth_xmc4xxx_mask_unused_interrupts()
759 	regs->INTERRUPT_MASK = ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk;  in eth_xmc4xxx_mask_unused_interrupts()
762 static inline int eth_xmc4xxx_init_timestamp_control_reg(ETH_GLOBAL_TypeDef *regs)  in eth_xmc4xxx_init_timestamp_control_reg()  argument
765 	regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk |  in eth_xmc4xxx_init_timestamp_control_reg()
771 	regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk |  in eth_xmc4xxx_init_timestamp_control_reg()
776 	regs->SUB_SECOND_INCREMENT = 20;  in eth_xmc4xxx_init_timestamp_control_reg()
784 	regs->TIMESTAMP_ADDEND = K;  in eth_xmc4xxx_init_timestamp_control_reg()
787 	regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;  in eth_xmc4xxx_init_timestamp_control_reg()
788 	if (!WAIT_FOR((regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk) == 0,  in eth_xmc4xxx_init_timestamp_control_reg()
793 	regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;  in eth_xmc4xxx_init_timestamp_control_reg()
794 	if (!WAIT_FOR((regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk) == 0,  in eth_xmc4xxx_init_timestamp_control_reg()
839 	dev_cfg->regs->MAC_CONFIGURATION = ETH_MAC_CONFIGURATION_IPC_Msk;  in eth_xmc4xxx_init()
842 	dev_cfg->regs->MAC_CONFIGURATION &= ~ETH_MAC_CONFIGURATION_JE_Msk;  in eth_xmc4xxx_init()
846 	dev_cfg->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk;  in eth_xmc4xxx_init()
850 	dev_cfg->regs->OPERATION_MODE = ETH_OPERATION_MODE_RSF_Msk | ETH_OPERATION_MODE_TSF_Msk |  in eth_xmc4xxx_init()
855 	dev_cfg->regs->BUS_MODE = ETH_BUS_MODE_ATDS_Msk | ETH_BUS_MODE_AAL_Msk |  in eth_xmc4xxx_init()
865 	dev_cfg->regs->STATUS = ETH_STATUS_CLEARABLE_BITS;  in eth_xmc4xxx_init()
867 	eth_xmc4xxx_mask_unused_interrupts(dev_cfg->regs);  in eth_xmc4xxx_init()
872 	eth_xmc4xxx_set_mac_address(dev_cfg->regs, dev_data->mac_addr);  in eth_xmc4xxx_init()
874 	uint32_t reg = dev_cfg->regs->MAC_FRAME_FILTER;  in eth_xmc4xxx_init()
879 	dev_cfg->regs->MAC_FRAME_FILTER = reg;  in eth_xmc4xxx_init()
881 	return eth_xmc4xxx_init_timestamp_control_reg(dev_cfg->regs);  in eth_xmc4xxx_init()
914 		eth_xmc4xxx_set_mac_address(dev_cfg->regs, dev_data->mac_addr);  in eth_xmc4xxx_set_config()
952 		dev_cfg->regs->VLAN_TAG = FIELD_PREP(ETH_VLAN_TAG_VL_Msk, tag) |  in eth_xmc4xxx_vlan_setup()
955 		dev_cfg->regs->MAC_FRAME_FILTER |= ETH_MAC_FRAME_FILTER_VTFE_Msk;  in eth_xmc4xxx_vlan_setup()
957 		dev_cfg->regs->VLAN_TAG = 0;  in eth_xmc4xxx_vlan_setup()
958 		dev_cfg->regs->MAC_FRAME_FILTER &= ~ETH_MAC_FRAME_FILTER_VTFE_Msk;  in eth_xmc4xxx_vlan_setup()
985 	.regs = (ETH_GLOBAL_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(0)),
1024 	dev_cfg->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = tm->nanosecond;  in eth_xmc4xxx_ptp_clock_set()
1025 	dev_cfg->regs->SYSTEM_TIME_SECONDS_UPDATE = tm->second;  in eth_xmc4xxx_ptp_clock_set()
1027 	dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;  in eth_xmc4xxx_ptp_clock_set()
1028 	if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk) == 0,  in eth_xmc4xxx_ptp_clock_set()
1041 	uint32_t nanosecond_0 = dev_cfg->regs->SYSTEM_TIME_NANOSECONDS;  in eth_xmc4xxx_ptp_clock_get()
1042 	uint32_t second_0 = dev_cfg->regs->SYSTEM_TIME_SECONDS;  in eth_xmc4xxx_ptp_clock_get()
1044 	uint32_t nanosecond_1 = dev_cfg->regs->SYSTEM_TIME_NANOSECONDS;  in eth_xmc4xxx_ptp_clock_get()
1045 	uint32_t second_1 = dev_cfg->regs->SYSTEM_TIME_SECONDS;  in eth_xmc4xxx_ptp_clock_get()
1077 	dev_cfg->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = increment_tmp;  in eth_xmc4xxx_ptp_clock_adjust()
1078 	dev_cfg->regs->SYSTEM_TIME_SECONDS_UPDATE = 0;  in eth_xmc4xxx_ptp_clock_adjust()
1080 	dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSUPDT_Msk;  in eth_xmc4xxx_ptp_clock_adjust()
1081 	if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSUPDT_Msk) == 0,  in eth_xmc4xxx_ptp_clock_adjust()
1093 	uint64_t K = dev_cfg->regs->TIMESTAMP_ADDEND;  in eth_xmc4xxx_ptp_clock_rate_adjust()
1104 	dev_cfg->regs->TIMESTAMP_ADDEND = K;  in eth_xmc4xxx_ptp_clock_rate_adjust()
1107 	dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;  in eth_xmc4xxx_ptp_clock_rate_adjust()
1108 	if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk) == 0,  in eth_xmc4xxx_ptp_clock_rate_adjust()