1 /*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT intel_cavs_intc
8
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/device.h>
11 #include <zephyr/devicetree/interrupt_controller.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/irq_nextlevel.h>
14 #include <zephyr/arch/arch_interface.h>
15 #include <zephyr/sw_isr_table.h>
16 #include "intc_cavs.h"
17
18 #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
19 #if defined(CONFIG_SOC_INTEL_CAVS_V25)
20 #define PER_CPU_OFFSET(x) (0x40 * x)
21 #else
22 #error "Must define PER_CPU_OFFSET(x) for SoC"
23 #endif
24 #else
25 #define PER_CPU_OFFSET(x) 0
26 #endif
27
28 static ALWAYS_INLINE
get_base_address(struct cavs_ictl_runtime * context)29 struct cavs_registers *get_base_address(struct cavs_ictl_runtime *context)
30 {
31 #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
32 return UINT_TO_POINTER(context->base_addr +
33 PER_CPU_OFFSET(arch_curr_cpu()->id));
34 #else
35 return UINT_TO_POINTER(context->base_addr);
36 #endif
37 }
38
cavs_ictl_dispatch_child_isrs(uint32_t intr_status,uint32_t isr_base_offset)39 static ALWAYS_INLINE void cavs_ictl_dispatch_child_isrs(uint32_t intr_status,
40 uint32_t isr_base_offset)
41 {
42 uint32_t intr_bitpos, intr_offset;
43
44 /* Dispatch lower level ISRs depending upon the bit set */
45 while (intr_status) {
46 intr_bitpos = find_lsb_set(intr_status) - 1;
47 intr_status &= ~(1 << intr_bitpos);
48 intr_offset = isr_base_offset + intr_bitpos;
49 _sw_isr_table[intr_offset].isr(
50 _sw_isr_table[intr_offset].arg);
51 }
52 }
53
cavs_ictl_isr(const struct device * port)54 static void cavs_ictl_isr(const struct device *port)
55 {
56 struct cavs_ictl_runtime *context = port->data;
57
58 const struct cavs_ictl_config *config = port->config;
59
60 volatile struct cavs_registers * const regs = get_base_address(context);
61
62 cavs_ictl_dispatch_child_isrs(regs->status_il,
63 config->isr_table_offset);
64 }
65
cavs_ictl_irq_enable(const struct device * dev,unsigned int irq)66 static void cavs_ictl_irq_enable(const struct device *dev,
67 unsigned int irq)
68 {
69 struct cavs_ictl_runtime *context = dev->data;
70
71 volatile struct cavs_registers * const regs = get_base_address(context);
72
73 regs->enable_il = 1 << irq;
74 }
75
cavs_ictl_irq_disable(const struct device * dev,unsigned int irq)76 static void cavs_ictl_irq_disable(const struct device *dev,
77 unsigned int irq)
78 {
79 struct cavs_ictl_runtime *context = dev->data;
80
81 volatile struct cavs_registers * const regs = get_base_address(context);
82
83 regs->disable_il = 1 << irq;
84 }
85
cavs_ictl_irq_get_state(const struct device * dev)86 static unsigned int cavs_ictl_irq_get_state(const struct device *dev)
87 {
88 struct cavs_ictl_runtime *context = dev->data;
89
90 volatile struct cavs_registers * const regs = get_base_address(context);
91
92 /* When the bits of this register are set, it means the
93 * corresponding interrupts are disabled. This function
94 * returns 0 only if ALL the interrupts are disabled.
95 */
96 return regs->disable_state_il != 0xFFFFFFFF;
97 }
98
cavs_ictl_irq_get_line_state(const struct device * dev,unsigned int irq)99 static int cavs_ictl_irq_get_line_state(const struct device *dev,
100 unsigned int irq)
101 {
102 struct cavs_ictl_runtime *context = dev->data;
103
104 volatile struct cavs_registers * const regs = get_base_address(context);
105
106 if ((regs->disable_state_il & BIT(irq)) == 0) {
107 return 1;
108 }
109
110 return 0;
111 }
112
113 static const struct irq_next_level_api cavs_apis = {
114 .intr_enable = cavs_ictl_irq_enable,
115 .intr_disable = cavs_ictl_irq_disable,
116 .intr_get_state = cavs_ictl_irq_get_state,
117 .intr_get_line_state = cavs_ictl_irq_get_line_state,
118 };
119
120 #define CAVS_ICTL_INIT(n) \
121 static int cavs_ictl_##n##_initialize(const struct device *port) \
122 { \
123 struct cavs_ictl_runtime *context = port->data; \
124 volatile struct cavs_registers * const regs = \
125 get_base_address(context); \
126 regs->disable_il = ~0; \
127 \
128 return 0; \
129 } \
130 \
131 static void cavs_config_##n##_irq(const struct device *port); \
132 \
133 static const struct cavs_ictl_config cavs_config_##n = { \
134 .irq_num = DT_INST_IRQN(n), \
135 .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + \
136 CONFIG_MAX_IRQ_PER_AGGREGATOR*n, \
137 .config_func = cavs_config_##n##_irq, \
138 }; \
139 \
140 static struct cavs_ictl_runtime cavs_##n##_runtime = { \
141 .base_addr = DT_INST_REG_ADDR(n), \
142 }; \
143 DEVICE_DT_INST_DEFINE(n, \
144 cavs_ictl_##n##_initialize, \
145 NULL, \
146 &cavs_##n##_runtime, &cavs_config_##n, \
147 PRE_KERNEL_1, \
148 CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);\
149 \
150 static void cavs_config_##n##_irq(const struct device *port) \
151 { \
152 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
153 cavs_ictl_isr, DEVICE_DT_INST_GET(n), \
154 DT_INST_IRQ(n, sense)); \
155 } \
156 IRQ_PARENT_ENTRY_DEFINE( \
157 intc_cavs_##n, DEVICE_DT_INST_GET(n), DT_INST_IRQN(n), \
158 INTC_INST_ISR_TBL_OFFSET(n), \
159 DT_INST_INTC_GET_AGGREGATOR_LEVEL(n));
160
161 DT_INST_FOREACH_STATUS_OKAY(CAVS_ICTL_INIT)
162
