34 	SercomUsart *regs;  member
142 	SercomUsart * const regs = cfg->regs;  in uart_sam0_dma_tx_done()  local
144 	regs->INTENSET.reg = SERCOM_USART_INTENSET_TXC;  in uart_sam0_dma_tx_done()
231 	SercomUsart * const regs = cfg->regs;  in uart_sam0_dma_rx_done()  local
276 		   (uint32_t)(&(regs->DATA.reg)),  in uart_sam0_dma_rx_done()
287 		regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;  in uart_sam0_dma_rx_done()
310 	SercomUsart * const regs = cfg->regs;  in uart_sam0_rx_timeout()  local
342 		   (uint32_t)(&(regs->DATA.reg)),  in uart_sam0_rx_timeout()
347 	regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;  in uart_sam0_rx_timeout()
397 	SercomUsart * const usart = cfg->regs;  in uart_sam0_configure()
511 	SercomUsart * const usart = cfg->regs;  in uart_sam0_init()
643 	SercomUsart * const usart = config->regs;  in uart_sam0_poll_in()
657 	SercomUsart * const usart = config->regs;  in uart_sam0_poll_out()
670 	SercomUsart * const regs = config->regs;  in uart_sam0_err_check()  local
673 	if (regs->STATUS.reg & SERCOM_USART_STATUS_BUFOVF) {  in uart_sam0_err_check()
677 	if (regs->STATUS.reg & SERCOM_USART_STATUS_FERR) {  in uart_sam0_err_check()
681 	if (regs->STATUS.reg & SERCOM_USART_STATUS_PERR) {  in uart_sam0_err_check()
686 	if (regs->STATUS.reg & SERCOM_USART_STATUS_ISF) {  in uart_sam0_err_check()
690 	if (regs->STATUS.reg & SERCOM_USART_STATUS_COLL) {  in uart_sam0_err_check()
694 	regs->STATUS.reg |=	SERCOM_USART_STATUS_BUFOVF  in uart_sam0_err_check()
700 	regs->STATUS.reg |=	SERCOM_USART_STATUS_BUFOVF  in uart_sam0_err_check()
705 	wait_synchronization(regs);  in uart_sam0_err_check()
723 	SercomUsart * const regs = cfg->regs;  in uart_sam0_isr()  local
725 	if (dev_data->tx_len && regs->INTFLAG.bit.TXC) {  in uart_sam0_isr()
726 		regs->INTENCLR.reg = SERCOM_USART_INTENCLR_TXC;  in uart_sam0_isr()
750 	if (dev_data->rx_len && regs->INTFLAG.bit.RXC &&  in uart_sam0_isr()
753 		regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;  in uart_sam0_isr()
789 	SercomUsart *regs = config->regs;  in uart_sam0_fifo_fill()  local
791 	if (regs->INTFLAG.bit.DRE && len >= 1) {  in uart_sam0_fifo_fill()
792 		regs->DATA.reg = tx_data[0];  in uart_sam0_fifo_fill()
802 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_tx_enable()  local
804 	regs->INTENSET.reg = SERCOM_USART_INTENSET_DRE  in uart_sam0_irq_tx_enable()
811 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_tx_disable()  local
813 	regs->INTENCLR.reg = SERCOM_USART_INTENCLR_DRE  in uart_sam0_irq_tx_disable()
820 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_tx_ready()  local
822 	return (regs->INTFLAG.bit.DRE != 0) && (regs->INTENSET.bit.DRE != 0);  in uart_sam0_irq_tx_ready()
829 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_tx_complete()  local
831 	return (dev_data->txc_cache != 0) && (regs->INTENSET.bit.TXC != 0);  in uart_sam0_irq_tx_complete()
837 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_rx_enable()  local
839 	regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;  in uart_sam0_irq_rx_enable()
845 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_rx_disable()  local
847 	regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;  in uart_sam0_irq_rx_disable()
853 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_rx_ready()  local
855 	return regs->INTFLAG.bit.RXC != 0;  in uart_sam0_irq_rx_ready()
862 	SercomUsart * const regs = config->regs;  in uart_sam0_fifo_read()  local
864 	if (regs->INTFLAG.bit.RXC) {  in uart_sam0_fifo_read()
865 		uint8_t ch = regs->DATA.reg;  in uart_sam0_fifo_read()
880 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_is_pending()  local
882 	return (regs->INTENSET.reg & regs->INTFLAG.reg) != 0;  in uart_sam0_irq_is_pending()
889 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_err_enable()  local
891 	regs->INTENSET.reg |= SERCOM_USART_INTENCLR_ERROR;  in uart_sam0_irq_err_enable()
892 	wait_synchronization(regs);  in uart_sam0_irq_err_enable()
898 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_err_disable()  local
900 	regs->INTENCLR.reg |= SERCOM_USART_INTENSET_ERROR;  in uart_sam0_irq_err_disable()
901 	wait_synchronization(regs);  in uart_sam0_irq_err_disable()
909 	SercomUsart * const regs = config->regs;  in uart_sam0_irq_update()  local
919 	dev_data->txc_cache = regs->INTFLAG.bit.TXC;  in uart_sam0_irq_update()
920 	regs->INTFLAG.reg = SERCOM_USART_INTENCLR_ERROR  in uart_sam0_irq_update()
926 	regs->INTFLAG.reg = SERCOM_USART_INTENCLR_RXS;  in uart_sam0_irq_update()
972 	SercomUsart *regs = cfg->regs;  in uart_sam0_tx()  local
996 			    (uint32_t)(&(regs->DATA.reg)), len);  in uart_sam0_tx()
1032 	SercomUsart *regs = cfg->regs;  in uart_sam0_rx_enable()  local
1051 	while (regs->INTFLAG.bit.RXC) {  in uart_sam0_rx_enable()
1052 		char discard = regs->DATA.reg;  in uart_sam0_rx_enable()
1058 			    (uint32_t)(&(regs->DATA.reg)),  in uart_sam0_rx_enable()
1072 	regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;  in uart_sam0_rx_enable()
1118 	SercomUsart * const regs = cfg->regs;  in uart_sam0_rx_disable()  local
1130 	regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;  in uart_sam0_rx_disable()
1278 	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\
1292 	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\