Searched refs:msi (Results 26 – 50 of 50) sorted by relevance
12
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | l4_i2c1_sysclk_lptim1_lsi.overlay | 23 /delete-property/ msi-range;
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| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 26 /delete-property/ msi-range;
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| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 26 /delete-property/ msi-range;
|
| /Zephyr-latest/boards/st/nucleo_l552ze_q/ |
| D | nucleo_l552ze_q-common.dtsi | 51 msi-range = <6>;
|
| /Zephyr-latest/boards/st/stm32l4r9i_disco/ |
| D | stm32l4r9i_disco.dts | 68 msi-range = <6>;
69 msi-pll-mode;
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| /Zephyr-latest/boards/seeed/lora_e5_mini/ |
| D | lora_e5_mini.dts | 60 msi-range = <11>;
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| /Zephyr-latest/dts/arm/st/l0/ |
| D | stm32l0.dtsi | 64 clk_msi: clk-msi {
66 compatible = "st,stm32l0-msi-clock";
67 msi-range = <5>; /* 2.1MHz (reset value) */
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| /Zephyr-latest/boards/st/stm32l562e_dk/ |
| D | stm32l562e_dk_common.dtsi | 123 msi-range = <6>;
124 msi-pll-mode;
|
| /Zephyr-latest/boards/st/stm32u5a9j_dk/ |
| D | stm32u5a9j_dk.dts | 88 msi-range = <4>; /* 4MHz (reset value) */
89 msi-pll-mode;
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| /Zephyr-latest/boards/st/steval_stwinbx1/ |
| D | steval_stwinbx1.dts | 83 msi-range = <4>;
84 msi-pll-mode;
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| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l4.dtsi | 80 clk_msi: clk-msi {
82 compatible = "st,stm32-msi-clock";
83 msi-range = <6>; /* 4MHz (reset value) */
477 * clock to be enabled with msi-range = <11>;
|
| /Zephyr-latest/boards/st/disco_l475_iot1/ |
| D | disco_l475_iot1.dts | 96 msi-pll-mode;
97 msi-range = <11>; /* 48MHz USB bus clk */
|
| /Zephyr-latest/boards/st/sensortile_box_pro/ |
| D | sensortile_box_pro.dts | 89 msi-range = <4>;
90 msi-pll-mode;
|
| /Zephyr-latest/dts/arm/st/l1/ |
| D | stm32l1.dtsi | 55 clk_msi: clk-msi {
57 compatible = "st,stm32l0-msi-clock";
58 msi-range = <5>; /* 2.1MHz (reset value) */
|
| /Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/ |
| D | fvp_base_revc_2xaemv8a.dts | 92 its: msi-controller@2f020000 {
|
| /Zephyr-latest/dts/arm/st/u0/ |
| D | stm32u0.dtsi | 64 clk_msi: clk-msi {
66 compatible = "st,stm32-msi-clock";
67 msi-range = <4>; /* 4MHz (reset value) */
|
| /Zephyr-latest/dts/arm/st/wb/ |
| D | stm32wb.dtsi | 101 clk_msi: clk-msi {
103 compatible = "st,stm32-msi-clock";
104 msi-range = <6>; /* 4MHz (reset value) */
|
| /Zephyr-latest/dts/arm/st/wl/ |
| D | stm32wl.dtsi | 80 clk_msi: clk-msi {
82 compatible = "st,stm32-msi-clock";
83 msi-range = <6>; /* 4MHz (reset value) */
|
| /Zephyr-latest/boards/seeed/lora_e5_dev_board/ |
| D | lora_e5_dev_board.dts | 94 msi-range = <11>;
|
| /Zephyr-latest/include/zephyr/xen/public/ |
| D | domctl.h | 365 } msi; member
|
| /Zephyr-latest/dts/arm/st/l5/ |
| D | stm32l5.dtsi | 94 clk_msi: clk-msi {
96 compatible = "st,stm32-msi-clock";
97 msi-range = <6>; /* 4MHz (reset value) */
|
| /Zephyr-latest/dts/arm/st/u5/ |
| D | stm32u5.dtsi | 105 compatible = "st,stm32u5-msi-clock";
106 msi-range = <4>; /* 4MHz (reset value) */
112 compatible = "st,stm32u5-msi-clock";
113 msi-range = <4>; /* 4MHz (reset value) */
|
| /Zephyr-latest/dts/arm64/intel/ |
| D | intel_socfpga_agilex5.dtsi | 58 its: msi-controller@1d040000 {
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| /Zephyr-latest/dts/bindings/ |
| D | vendor-prefixes.txt | 442 msi Micro-Star International Co. Ltd.
|
| /Zephyr-latest/doc/releases/ |
| D | release-notes-2.7.rst | 873 :dtcompatible:`st,stm32u5-msi-clock`, :dtcompatible:`st,stm32u5-pll-clock`,
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