1/*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2023, Intel Corporation
5 *
6 */
7
8#include <arm64/armv8-a.dtsi>
9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10#include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
11#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
12#include <mem.h>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells= <0>;
18
19		cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-a55";
22			enable-method = "psci";
23			reg = <0x0>;
24		};
25
26		cpu@100 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a55";
29			enable-method = "psci";
30			reg = <0x100>;
31		};
32
33		cpu@200 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a76";
36			enable-method = "psci";
37			reg = <0x200>;
38		};
39
40		cpu@300 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a76";
43			enable-method = "psci";
44			reg = <0x300>;
45		};
46	};
47
48	gic: interrupt-controller@1d000000  {
49		compatible = "arm,gic-v3", "arm,gic";
50		reg = <0x1d000000 0x10000>, /* GICD */
51		      <0x1d060000 0x80000>; /* GICR */
52		interrupt-controller;
53		#interrupt-cells = <4>;
54		status = "okay";
55		#address-cells = <1>;
56		#size-cells = <1>;
57
58		its: msi-controller@1d040000 {
59			compatible = "arm,gic-v3-its";
60			reg = <0x1d040000 0x20000>;
61			status = "disabled";
62		};
63	};
64
65	arch_timer: timer {
66		compatible = "arm,armv8-timer";
67		interrupt-parent = <&gic>;
68		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
69			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
70			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
71			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
72	};
73
74	sysmgr: sysmgr@10d12000 {
75		compatible = "syscon";
76		reg = <0x10d12000 0x1000>;
77	};
78
79	clock: clock@10d10000 {
80		compatible = "intel,agilex5-clock";
81		reg = <0x10d10000 0x1000>;
82		#clock-cells = <1>;
83	};
84
85	psci {
86		compatible = "arm,psci-1.1";
87		method = "smc";
88	};
89
90	/* This is for setting the MMU region for pinmux */
91	pinmux: pinmux@10d13000 {
92		compatible = "syscon";
93		reg = <0x10d13000 0x1000>;
94	};
95
96	mem0: memory@80100000 {
97		device_type = "memory";
98		reg = <0x80100000 DT_SIZE_M(8)>;
99	};
100
101	fpga0: bridges {
102		compatible = "altr,socfpga-agilex-bridge";
103	};
104
105	uart0: uart@10c02000 {
106		compatible = "ns16550";
107		reg-shift = <2>;
108		reg = <0x10c02000 0x100>;
109		interrupt-parent = <&gic>;
110		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
111		interrupt-names = "irq_0";
112		clocks = <&clock INTEL_SOCFPGA_CLOCK_UART>;
113		resets = <&reset RSTMGR_UART0_RSTLINE>;
114		status = "disabled";
115	};
116
117	reset: reset-controller@10D11000 {
118		compatible = "intel,socfpga-reset";
119		reg = <0x10D11000 0x100>;
120		active-low;
121		#reset-cells = <1>;
122		status = "okay";
123	};
124
125	sdmmc: sdmmc@10808000 {
126		compatible = "cdns,sdhc";
127		reg = <0x10808000 0x1000>,
128			<0x10B92000 0x1000>;
129		reg-names = "reg_base", "combo_phy";
130		clock-frequency = <200000000>;
131		power_delay_ms = <1000>;
132		resets = <&reset RSTMGR_SDMMC_RSTLINE>,
133			<&reset RSTMGR_SDMMCECC_RSTLINE>,
134			<&reset RSTMGR_SOFTPHY_RSTLINE>;
135		status = "disabled";
136	};
137
138	timer0: timer@10C03000 {
139		compatible = "snps,dw-timers";
140		interrupt-parent = <&gic>;
141		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL
142				IRQ_DEFAULT_PRIORITY>;
143		reg = <0x10c03000 0x100>;
144		clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>;
145		resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
146		status = "disabled";
147	};
148
149	timer1: timer@10C03100 {
150		compatible = "snps,dw-timers";
151		interrupt-parent = <&gic>;
152		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL
153				IRQ_DEFAULT_PRIORITY>;
154		reg = <0x10c03100 0x100>;
155		clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>;
156		resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
157		status = "disabled";
158	};
159
160	timer2: timer@10D00000 {
161		compatible = "snps,dw-timers";
162		interrupt-parent = <&gic>;
163		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL
164				IRQ_DEFAULT_PRIORITY>;
165		reg = <0x10D00000 0x100>;
166		clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>;
167		resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>;
168		status = "disabled";
169	};
170
171	timer3: timer@10D00100 {
172		compatible = "snps,dw-timers";
173		interrupt-parent = <&gic>;
174		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL
175				IRQ_DEFAULT_PRIORITY>;
176		reg = <0x10D00100 0x100>;
177		clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>;
178		resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>;
179	};
180
181	watchdog0: watchdog@10d00200 {
182		compatible = "snps,designware-watchdog";
183		reg = <0x10d00200 0x100>;
184		clock-frequency = <100000000>;
185		resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>;
186		status = "disabled";
187	};
188
189	watchdog1: watchdog@10d00300 {
190		compatible = "snps,designware-watchdog";
191		reg = <0x10d00300 0x100>;
192		clock-frequency = <100000000>;
193		resets = <&reset RSTMGR_WATCHDOG1_RSTLINE>;
194		status = "disabled";
195	};
196
197	watchdog2: watchdog@10d00400 {
198		compatible = "snps,designware-watchdog";
199		reg = <0x10d00400 0x100>;
200		clock-frequency = <100000000>;
201		resets = <&reset RSTMGR_WATCHDOG2_RSTLINE>;
202		status = "disabled";
203	};
204
205	watchdog3: watchdog@10d00500 {
206		compatible = "snps,designware-watchdog";
207		reg = <0x10d00500 0x100>;
208		clock-frequency = <100000000>;
209		resets = <&reset RSTMGR_WATCHDOG3_RSTLINE>;
210		status = "disabled";
211	};
212
213	watchdog4: watchdog@10d00600 {
214		compatible = "snps,designware-watchdog";
215		reg = <0x10d00600 0x100>;
216		clock-frequency = <100000000>;
217		resets = <&reset RSTMGR_WATCHDOG4_RSTLINE>;
218		status = "disabled";
219	};
220
221	sip_smc: smc{
222		compatible = "intel,socfpga-agilex-sip-smc";
223		method = "smc";
224		status = "disabled";
225		zephyr,num-clients = <2>;
226	};
227
228	/* cadence Nand Flash controller*/
229	nand: nand@10B80000	{
230		compatible = "cdns,nand";
231		reg = <0x10B80000 0X10000>,
232			  <0x10840000 0x10000>;
233		reg-names = "nand_reg","sdma";
234		interrupt-parent = <&gic>;
235		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
236		resets = <&reset RSTMGR_NAND_RSTLINE>,
237				<&reset RSTMGR_SOFTPHY_RSTLINE>;
238		block-size = <0x20000>;
239		data-rate-mode = <0>;
240		status = "disabled";
241	};
242
243	dma0: dma@10DB0000 {
244		compatible = "snps,designware-dma-axi";
245		#dma-cells = <1>;
246		reg = <0x10DB0000 0x1000>;
247		interrupt-parent = <&gic>;
248		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL
249				 IRQ_DEFAULT_PRIORITY>,
250			     <GIC_SPI 82 IRQ_TYPE_LEVEL
251				 IRQ_DEFAULT_PRIORITY>,
252			     <GIC_SPI 83 IRQ_TYPE_LEVEL
253				 IRQ_DEFAULT_PRIORITY>,
254			     <GIC_SPI 84 IRQ_TYPE_LEVEL
255				 IRQ_DEFAULT_PRIORITY>;
256		dma-channels = <4>;
257		resets = <&reset RSTMGR_DMA_RSTLINE>;
258		status = "disabled";
259	};
260
261	dma1: dma@10DC0000 {
262		compatible = "snps,designware-dma-axi";
263		#dma-cells = <1>;
264		reg = <0x10DC0000 0x1000>;
265		interrupt-parent = <&gic>;
266		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL
267				 IRQ_DEFAULT_PRIORITY>,
268			     <GIC_SPI 167 IRQ_TYPE_LEVEL
269				 IRQ_DEFAULT_PRIORITY>,
270			     <GIC_SPI 168 IRQ_TYPE_LEVEL
271				 IRQ_DEFAULT_PRIORITY>,
272			     <GIC_SPI 169 IRQ_TYPE_LEVEL
273				 IRQ_DEFAULT_PRIORITY>;
274		dma-channels = <4>;
275		resets = <&reset RSTMGR_DMA_RSTLINE>;
276	};
277
278	xgmac0: xgmac@10810000 {
279		compatible = "snps,dwcxgmac";
280		reg = <0x10810000 0x10000>;
281		interrupt-parent = <&gic>;
282		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL
283			      IRQ_DEFAULT_PRIORITY>;
284		local-mac-address = [06 00 00 00 00 01];
285		max-frame-size = <1518>;
286		tx-fifo-size = <32768>;
287		rx-fifo-size = <16384>;
288		pblx8;
289		blen32;
290		status = "disabled";
291	};
292
293	mdio0: mdio@10810000 {
294		#address-cells = <1>;
295		#size-cells = <0>;
296		reg = <0x10810000 0x10000>;
297		resets = <&reset RSTMGR_TSN0_RSTLINE>;
298		compatible = "snps,dwcxgmac-mdio";
299		status = "disabled";
300	};
301
302	xgmac1: xgmac@10820000 {
303		compatible = "snps,dwcxgmac";
304		reg = <0x10820000 0x10000>;
305		interrupt-parent = <&gic>;
306		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL
307			      IRQ_DEFAULT_PRIORITY>;
308		local-mac-address = [06 00 00 00 00 02];
309		max-frame-size = <1518>;
310		tx-fifo-size = <32768>;
311		rx-fifo-size = <16384>;
312		pblx8;
313		blen32;
314		status = "disabled";
315	};
316
317	mdio1: mdio@10820000 {
318		#address-cells = <1>;
319		#size-cells = <0>;
320		reg = <0x10820000 0x10000>;
321		resets = <&reset RSTMGR_TSN1_RSTLINE>;
322		compatible = "snps,dwcxgmac-mdio";
323		status = "disabled";
324	};
325
326	xgmac2: xgmac@10830000 {
327		compatible = "snps,dwcxgmac";
328		reg = <0x10830000 0x10000>;
329		interrupt-parent = <&gic>;
330		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL
331			      IRQ_DEFAULT_PRIORITY>;
332		local-mac-address = [06 00 00 00 00 03];
333		max-frame-size = <1518>;
334		tx-fifo-size = <32768>;
335		rx-fifo-size = <16384>;
336		pblx8;
337		blen32;
338		status = "disabled";
339	};
340
341	mdio2: mdio@10830000 {
342		#address-cells = <1>;
343		#size-cells = <0>;
344		reg = <0x10830000 0x10000>;
345		resets = <&reset RSTMGR_TSN2_RSTLINE>;
346		compatible = "snps,dwcxgmac-mdio";
347		status = "disabled";
348	};
349};
350