1/*
2 * Copyright (c) 2020 Yestin Sun
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l5/stm32l562Xe.dtsi>
8#include <st/l5/stm32l562qeixq-pinctrl.dtsi>
9#include "arduino_r3_connector.dtsi"
10#include <zephyr/dt-bindings/input/input-event-codes.h>
11#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
12#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
13
14/ {
15	leds {
16		compatible = "gpio-leds";
17		red_led_9: led_9 {
18			gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
19			label = "User LD9";
20		};
21		green_led_10: led_10 {
22			gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
23			label = "User LD10";
24		};
25	};
26
27	gpio_keys {
28		compatible = "gpio-keys";
29		user_button: button {
30			label = "User";
31			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
32			zephyr,code = <INPUT_KEY_0>;
33		};
34	};
35
36	aliases {
37		die-temp0 = &die_temp;
38		volt-sensor0 = &vref;
39		volt-sensor1 = &vbat;
40	};
41
42	chosen {
43		zephyr,bt-hci = &hci_spi;
44	};
45};
46
47&fmc {
48	pinctrl-0 = <&fmc_a0_pf0 &fmc_nce_pd7 &fmc_nwe_pd5 &fmc_noe_pd4
49		     &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
50		     &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
51		     &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
52		     &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
53	pinctrl-names = "default";
54	status = "okay";
55
56	sram {
57		compatible = "st,stm32-fmc-nor-psram";
58
59		#address-cells = <1>;
60		#size-cells = <0>;
61
62		bank@0 {
63			reg = <0x0>;
64			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
65				STM32_FMC_MEMORY_TYPE_SRAM
66				STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
67				STM32_FMC_BURST_ACCESS_MODE_DISABLE
68				STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
69				STM32_FMC_WAIT_TIMING_BEFORE_WS
70				STM32_FMC_WRITE_OPERATION_ENABLE
71				STM32_FMC_WAIT_SIGNAL_DISABLE
72				STM32_FMC_EXTENDED_MODE_DISABLE
73				STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
74				STM32_FMC_WRITE_BURST_DISABLE
75				STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
76				STM32_FMC_WRITE_FIFO_DISABLE
77				STM32_FMC_PAGE_SIZE_NONE>;
78			st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>;
79
80			fmc-mipi-dbi {
81				compatible = "st,stm32-fmc-mipi-dbi";
82				reset-gpios = <&gpiof 14 GPIO_ACTIVE_LOW>;
83				power-gpios = <&gpioh 0 GPIO_ACTIVE_LOW>;
84				register-select-pin = <0>;
85				#address-cells = <1>;
86				#size-cells = <0>;
87				st7789v: lcd-panel@0 {
88					compatible = "sitronix,st7789v";
89					reg = <0>;
90					mipi-mode = "MIPI_DBI_MODE_8080_BUS_16_BIT";
91					/* A write cycle should be 68ns */
92					mipi-max-frequency = <14705882>;
93					width = <240>;
94					height = <240>;
95					x-offset = <0>;
96					y-offset = <0>;
97					vcom = <0x1F>;
98					gctrl = <0x35>;
99					vdvs = <0x20>;
100					mdac = <0x00>;
101					gamma = <0x01>;
102					colmod = <0x05>;
103					lcm = <0x2c>;
104					porch-param = [0c 0c 00 33 33];
105					cmd2en-param = [5a 69 02 00];
106					pwctrl1-param = [a4 a1];
107					pvgam-param = [D0 08 11 08 0C 15 39 33 50 36 13 14 29 2D];
108					nvgam-param = [D0 08 10 08 06 06 39 44 51 0B 16 14 2F 31];
109					ram-param = [00 F0];
110					rgb-param = [40 02 14];
111				};
112			};
113		};
114	};
115};
116
117&clk_hsi48 {
118	status = "okay";
119};
120
121&clk_msi {
122	status = "okay";
123	msi-range = <6>;
124	msi-pll-mode;
125};
126
127&clk_lse {
128	status = "okay";
129};
130
131&pll {
132	div-m = <1>;
133	mul-n = <55>;
134	div-p = <7>;
135	div-q = <2>;
136	div-r = <2>;
137	clocks = <&clk_msi>;
138	status = "okay";
139};
140
141&rcc {
142	clocks = <&pll>;
143	clock-frequency = <DT_FREQ_M(110)>;
144	ahb-prescaler = <1>;
145	apb1-prescaler = <1>;
146	apb2-prescaler = <1>;
147};
148
149stm32_lp_tick_source: &lptim1 {
150	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
151		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
152	status = "okay";
153};
154
155&usart1 {
156	current-speed = <115200>;
157	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
158	pinctrl-names = "default";
159	status = "okay";
160};
161
162&usart3 {
163	pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
164	pinctrl-names = "default";
165	current-speed = <115200>;
166	status = "okay";
167};
168
169&i2c1 {
170	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
171	pinctrl-names = "default";
172	status = "okay";
173	clock-frequency = <I2C_BITRATE_FAST>;
174
175	lsm6dso: lsm6dso@6a {
176		compatible = "st,lsm6dso";
177		reg = <0x6a>;
178		irq-gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
179	};
180};
181
182&rng {
183	status = "okay";
184};
185
186&spi1 {
187	pinctrl-0 = <&spi1_sck_pg2 &spi1_miso_pg3 &spi1_mosi_pg4>;
188	pinctrl-names = "default";
189	cs-gpios = <&gpiog 5 GPIO_ACTIVE_LOW>;
190	status = "okay";
191
192	hci_spi: spbtle-rf@0 {
193		compatible = "st,hci-spi-v1";
194		reg = <0>;
195		irq-gpios = <&gpiog 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
196		reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
197		spi-max-frequency = <DT_FREQ_M(2)>;
198		spi-hold-cs;
199	};
200};
201
202&octospi1 {
203	pinctrl-0 = <&octospi1_clk_pa3 &octospi1_ncs_pa2
204		     &octospi1_io0_pb1 &octospi1_io1_pb0
205		     &octospi1_io2_pa7 &octospi1_io3_pa6
206		     &octospi1_io4_pc1 &octospi1_io5_pc2
207		     &octospi1_io6_pc3 &octospi1_io7_pc0
208		     &octospi1_dqs_pb2>;
209	pinctrl-names = "default";
210
211	status = "okay";
212
213	mx25lm51245: ospi-nor-flash@90000000 {
214		compatible = "st,stm32-ospi-nor";
215		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
216		ospi-max-frequency = <DT_FREQ_M(50)>;
217		spi-bus-width = <OSPI_OPI_MODE>;
218		data-rate = <OSPI_DTR_TRANSFER>;
219		four-byte-opcodes;
220		status = "okay";
221		sfdp-bfp = [
222			53 46 44 50 06 01 02 ff
223			00 06 01 10 30 00 00 ff
224			c2 00 01 04 10 01 00 ff
225			84 00 01 02 c0 00 00 ff
226			00 00 00 00 00 00 00 00
227			00 00 00 00 00 00 00 00
228			e5 20 fb ff ff ff ff 1f
229			44 eb 08 6b 08 3b 04 bb
230			fe ff ff ff ff ff 00 ff
231			ff ff 44 eb 0c 20 0f 52
232			10 d8 00 ff d6 49 c5 00
233			81 df 04 e3 44 03 67 38
234			30 b0 30 b0 f7 bd d5 5c
235			4a 9e 29 ff f0 50 f9 85
236			00 00 00 00 00 00 00 00
237			00 00 00 00 00 00 00 00
238			00 00 00 00 00 00 00 00
239			00 00 00 00 00 00 00 00
240			00 00 00 00 00 00 00 00
241			00 00 00 00 00 00 00 00
242			00 00 00 00 00 00 00 00
243			00 00 00 00 00 00 00 00
244			00 00 00 00 00 00 00 00
245			00 00 00 00 00 00 00 00
246			7f ef ff ff 21 5c dc ff
247		];
248
249		partitions {
250			compatible = "fixed-partitions";
251			#address-cells = <1>;
252			#size-cells = <1>;
253
254			partition@0 {
255				reg = <0x00000000 DT_SIZE_M(64)>;
256			};
257		};
258	};
259};
260
261&timers2 {
262	status = "okay";
263
264	pwm2: pwm {
265		status = "okay";
266		pinctrl-0 = <&tim2_ch1_pa0>;
267		pinctrl-names = "default";
268	};
269};
270
271&dac1 {
272	status = "okay";
273	pinctrl-0 = <&dac1_out1_pa4>;
274	pinctrl-names = "default";
275};
276
277&adc1 {
278	pinctrl-0 = <&adc1_in13_pc4>;
279	pinctrl-names = "default";
280	st,adc-clock-source = "SYNC";
281	st,adc-prescaler = <4>;
282	status = "okay";
283};
284
285&die_temp {
286	status = "okay";
287};
288
289&spi3 {
290	pinctrl-0 = <&spi3_sck_pg9 &spi3_mosi_pb5 &spi3_miso_pb4>;
291	pinctrl-names = "default";
292	cs-gpios = <&gpioe 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
293	status = "okay";
294};
295
296zephyr_udc0: &usb {
297	pinctrl-0 = <&usb_dp_pa12 &usb_dm_pa11>;
298	pinctrl-names = "default";
299	status = "okay";
300};
301
302&sdmmc1 {
303	status = "okay";
304
305	pinctrl-0 = <&sdmmc1_d0_pc8
306		     &sdmmc1_d1_pc9
307		     &sdmmc1_d2_pc10
308		     &sdmmc1_d3_pc11
309		     &sdmmc1_ck_pc12
310		     &sdmmc1_cmd_pd2>;
311
312	pinctrl-names = "default";
313
314	cd-gpios = <&gpiof 2 GPIO_ACTIVE_LOW>;
315};
316
317&vref {
318	status = "okay";
319};
320
321&vbat {
322	status = "okay";
323};
324