| /Zephyr-latest/dts/arm/microchip/mec172x/ |
| D | mec172x-vw-routing.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 mchp-xec-espi-vw-routing {
12 compatible = "microchip,xec-espi-vw-routing";
16 /* Host-index MSVW/SMVW MSVW/SMVW-index source */
17 vw-reg = <0x02 MSVW 0 0>;
18 vw-girq = <24 0>;
19 status = "okay";
22 vw-reg = <0x02 MSVW 0 1>;
23 vw-girq = <24 1>;
24 status = "okay";
[all …]
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| /Zephyr-latest/dts/arm/microchip/ |
| D | mec5.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
21 reg = <0>;
27 reg = <0x4000fc00 0x200>;
28 status = "disabled";
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat1a/psoc6_01/ |
| D | psoc6_01.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
18 reg = <0>;
22 compatible = "arm,cortex-m4f";
23 reg = <1>;
27 flash-controller@40250000 {
28 compatible = "infineon,cat1-flash-controller";
29 reg = < 0x40250000 0x10000 >;
[all …]
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| /Zephyr-latest/drivers/sensor/st/vl53l1x/ |
| D | vl53l1_platform.c | 1 /* vl53l1_platform.c - Zephyr customization of ST vl53l1x library.
7 * SPDX-License-Identifier: Apache-2.0
23 VL53L1_Error VL53L1_WriteMulti(VL53L1_Dev_t *pdev, uint16_t reg, in VL53L1_WriteMulti() argument
26 VL53L1_Error status = VL53L1_ERROR_NONE; in VL53L1_WriteMulti() local
30 /* To be able to write to the 16-bit registers/addresses on the vl53l1x */ in VL53L1_WriteMulti()
31 buffer[1] = (uint8_t)(reg & 0x00ff); in VL53L1_WriteMulti()
32 buffer[0] = (uint8_t)((reg & 0xff00) >> 8); in VL53L1_WriteMulti()
36 status_int = i2c_write_dt(pdev->i2c, buffer, count + 2); in VL53L1_WriteMulti()
39 status = VL53L1_ERROR_CONTROL_INTERFACE; in VL53L1_WriteMulti()
43 return status; in VL53L1_WriteMulti()
[all …]
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| /Zephyr-latest/dts/arm/ene/ |
| D | kb1200.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-m4";
23 reg = <0>;
24 clock-frequency = <DT_FREQ_M(48)>;
29 compatible = "mmio-sram";
30 reg = <0x20040000 0x10000>;
34 flash-controller@50100000 {
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat1a/psoc6_02/ |
| D | psoc6_02.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
18 reg = <0>;
22 compatible = "arm,cortex-m4f";
23 reg = <1>;
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
29 reg = < 0x40240000 0x10000 >;
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat3/xmc/ |
| D | xmc4xxx.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m4f";
20 reg = <0>;
25 compatible = "infineon,xmc4xxx-flash-controller";
[all …]
|
| /Zephyr-latest/dts/arm/nordic/ |
| D | nrf51822.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv6-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-adc.h>
9 zephyr,bt-hci = &bt_hci_controller;
11 zephyr,flash-controller = &flash_controller;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0";
21 reg = <0>;
27 compatible = "nordic,nrf-ficr";
[all …]
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| D | nrf52810.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
22 reg = <0>;
[all …]
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| D | nrf5340_cpuapp_peripherals.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 compatible = "nordic,nrf-dcnf";
11 reg = <0x0 0x1000>;
12 status = "okay";
15 oscillators: clock-controller@4000 {
16 compatible = "nordic,nrf53-oscillators";
17 reg = <0x4000 0x1000>;
20 compatible = "nordic,nrf53-lfxo";
21 #clock-cells = <0>;
[all …]
|
| D | nrf52832.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4f";
22 reg = <0>;
[all …]
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| D | nrf52805.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
14 zephyr,bt-hci = &bt_hci_controller;
16 zephyr,flash-controller = &flash_controller;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-m4";
26 reg = <0>;
[all …]
|
| D | nrf5340_cpunet.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
12 zephyr,bt-hci = &bt_hci_controller;
14 zephyr,flash-controller = &flash_controller;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-m33";
24 reg = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
[all …]
|
| D | nrf91_peripherals.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 flash_controller: flash-controller@39000 {
8 compatible = "nordic,nrf91-flash-controller";
9 reg = <0x39000 0x1000>;
10 partial-erase;
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "soc-nv-flash";
18 erase-block-size = <4096>;
19 write-block-size = <4>;
[all …]
|
| D | nrf52840.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4f";
22 reg = <0>;
[all …]
|
| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_cavs25.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx6";
18 reg = <0>;
19 cpu-power-states = <&d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx6";
27 reg = <1>;
[all …]
|
| /Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/ |
| D | cyw20829.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m33";
18 reg = <0>;
19 cpu-power-states = <&idle &suspend_to_ram>;
22 power-states {
24 compatible = "zephyr,power-state";
25 power-state-name = "suspend-to-idle";
26 min-residency-us = <1000000>;
[all …]
|
| /Zephyr-latest/dts/arm/renesas/ra/ra4/ |
| D | ra4-cm33-common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m33";
21 reg = <0>;
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
|
| D | ra4-cm4-common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
21 reg = <0>;
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
|
| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | ra6-cm33-common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/clock/ra_clock.h>
11 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
22 reg = <0>;
23 #address-cells = <1>;
[all …]
|
| /Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/ |
| D | psoc6_04.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
18 reg = <0>;
22 compatible = "arm,cortex-m4f";
23 reg = <1>;
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
29 reg = < 0x40240000 0x10000 >;
[all …]
|
| /Zephyr-latest/dts/arm/renesas/ra/ra2/ |
| D | ra2xx.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/clock/ra_clock.h>
11 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m23";
22 reg = <0>;
28 compatible = "renesas,ra-system";
[all …]
|
| /Zephyr-latest/dts/common/nordic/ |
| D | nrf54l_05_10_15.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
12 /delete-node/ &sw_pwm;
19 #address-cells = <1>;
20 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "arm,cortex-m33f";
28 reg = <0>;
[all …]
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| D | nrf54l20.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
12 /delete-node/ &sw_pwm;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-m33f";
24 reg = <0>;
[all …]
|
| /Zephyr-latest/dts/arm/infineon/cat1a/legacy/ |
| D | psoc6_cm0.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
13 compatible = "arm,cortex-m0+";
16 /delete-node/ cpu@1;
21 /* see cypress,psoc6-int-mux.yaml */
22 compatible = "cypress,psoc6-intmux";
23 reg = <0x40210020 0x20>;
25 status = "okay";
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
|
