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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dch32v00x-clocks.h33 #define CH32V00X_CLOCK_TIM2 CH32V00X_CLOCK_CONFIG(APB1, 0)
34 #define CH32V00X_CLOCK_TIM3 CH32V00X_CLOCK_CONFIG(APB1, 1)
35 #define CH32V00X_CLOCK_WWDG CH32V00X_CLOCK_CONFIG(APB1, 11)
36 #define CH32V00X_CLOCK_USART2 CH32V00X_CLOCK_CONFIG(APB1, 17)
37 #define CH32V00X_CLOCK_I2C1 CH32V00X_CLOCK_CONFIG(APB1, 21)
38 #define CH32V00X_CLOCK_BKP CH32V00X_CLOCK_CONFIG(APB1, 27)
39 #define CH32V00X_CLOCK_PWR CH32V00X_CLOCK_CONFIG(APB1, 28)
40 #define CH32V00X_CLOCK_USB CH32V00X_CLOCK_CONFIG(APB1, 23)
/Zephyr-latest/samples/subsys/task_wdt/boards/
Dnucleo_f091rc.overlay8 * stm32F0 has a WWDG clock by APB1 where the APB1 prescaler is 1..16
9 * Adjust the APB1 clock to match the WDG timeout.
13 /delete-property/ apb1-prescaler;
14 apb1-prescaler = <16>;
/Zephyr-latest/dts/arm/st/f4/
Dstm32f413.dtsi16 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
17 resets = <&rctl STM32_RESET(APB1, 19U)>;
25 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
26 resets = <&rctl STM32_RESET(APB1, 20U)>;
34 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
35 resets = <&rctl STM32_RESET(APB1, 30U)>;
43 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
44 resets = <&rctl STM32_RESET(APB1, 31U)>;
70 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
80 clocks = <&rcc STM32_CLOCK(APB1, 27U)>;
Dstm32f405.dtsi49 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
50 resets = <&rctl STM32_RESET(APB1, 18U)>;
58 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
59 resets = <&rctl STM32_RESET(APB1, 19U)>;
67 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
68 resets = <&rctl STM32_RESET(APB1, 20U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
77 resets = <&rctl STM32_RESET(APB1, 4U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
93 resets = <&rctl STM32_RESET(APB1, 5U)>;
[all …]
Dstm32f412.dtsi54 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
55 resets = <&rctl STM32_RESET(APB1, 18U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
96 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
97 resets = <&rctl STM32_RESET(APB1, 5U)>;
135 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
136 resets = <&rctl STM32_RESET(APB1, 6U)>;
157 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
158 resets = <&rctl STM32_RESET(APB1, 7U)>;
179 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
[all …]
Dstm32f446.dtsi37 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
38 resets = <&rctl STM32_RESET(APB1, 18U)>;
46 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
47 resets = <&rctl STM32_RESET(APB1, 19U)>;
55 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
56 resets = <&rctl STM32_RESET(APB1, 20U)>;
66 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
146 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
/Zephyr-latest/dts/arm/st/f1/
Dstm32f105.dtsi42 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
59 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
67 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
68 resets = <&rctl STM32_RESET(APB1, 19U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
77 resets = <&rctl STM32_RESET(APB1, 20U)>;
87 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
97 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
105 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
[all …]
Dstm32f103Xc.dtsi29 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
30 resets = <&rctl STM32_RESET(APB1, 19U)>;
38 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
47 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
48 resets = <&rctl STM32_RESET(APB1, 3U)>;
64 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
76 resets = <&rctl STM32_RESET(APB1, 5U)>;
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f070Xb.dtsi31 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
32 resets = <&rctl STM32_RESET(APB1, 18U)>;
40 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
41 resets = <&rctl STM32_RESET(APB1, 19U)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
63 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
71 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
72 resets = <&rctl STM32_RESET(APB1, 4U)>;
82 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
83 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f030Xc.dtsi32 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
33 resets = <&rctl STM32_RESET(APB1, 18U)>;
41 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
42 resets = <&rctl STM32_RESET(APB1, 19U)>;
50 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
51 resets = <&rctl STM32_RESET(APB1, 20U)>;
68 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
69 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f051.dtsi16 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
17 resets = <&rctl STM32_RESET(APB1, 17U)>;
28 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
39 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
47 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
48 resets = <&rctl STM32_RESET(APB1, 4U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
Dstm32f071.dtsi47 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
48 resets = <&rctl STM32_RESET(APB1, 18U)>;
56 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
57 resets = <&rctl STM32_RESET(APB1, 19U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
66 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f030X8.dtsi24 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
25 resets = <&rctl STM32_RESET(APB1, 17U)>;
36 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
47 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
55 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
56 resets = <&rctl STM32_RESET(APB1, 4U)>;
Dstm32f042.dtsi27 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
28 resets = <&rctl STM32_RESET(APB1, 17U)>;
38 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
47 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
/Zephyr-latest/dts/arm/st/l0/
Dstm32l071.dtsi29 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
41 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
61 resets = <&rctl STM32_RESET(APB1, 1U)>;
82 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
83 resets = <&rctl STM32_RESET(APB1, 4U)>;
98 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
99 resets = <&rctl STM32_RESET(APB1, 5U)>;
145 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi38 clocks = <&rcc STM32_CLOCK(APB1, 22U)>,
53 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
63 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
71 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
72 resets = <&rctl STM32_RESET(APB1, 2U)>;
88 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
89 resets = <&rctl STM32_RESET(APB1, 3U)>;
105 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
106 resets = <&rctl STM32_RESET(APB1, 6U)>;
122 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
[all …]
Dstm32f3.dtsi179 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
196 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
197 resets = <&rctl STM32_RESET(APB1, 17U)>;
205 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
206 resets = <&rctl STM32_RESET(APB1, 18U)>;
214 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
215 resets = <&rctl STM32_RESET(APB1, 19U)>;
226 clocks = <&rcc STM32_CLOCK(APB1, 21U)>,
249 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
262 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
[all …]
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi203 clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
226 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
243 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
244 resets = <&rctl STM32_RESET(APB1, 17U)>;
252 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
253 resets = <&rctl STM32_RESET(APB1, 18U)>;
270 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
271 resets = <&rctl STM32_RESET(APB1, 19U)>;
279 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
280 resets = <&rctl STM32_RESET(APB1, 20U)>;
[all …]
/Zephyr-latest/dts/arm/st/g0/
Dstm32g0b1.dtsi41 clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
69 clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
78 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
87 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
107 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
118 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
147 clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
Dstm32g071.dtsi18 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
27 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
40 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
48 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi249 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
266 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
267 resets = <&rctl STM32_RESET(APB1, 17U)>;
275 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
276 resets = <&rctl STM32_RESET(APB1, 18U)>;
284 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
285 resets = <&rctl STM32_RESET(APB1, 19U)>;
293 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
294 resets = <&rctl STM32_RESET(APB1, 20U)>;
311 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
[all …]
/Zephyr-latest/dts/arm/st/mp1/
Dstm32mp157.dtsi176 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
230 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
240 clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
268 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
269 resets = <&rctl STM32_RESET(APB1, 14U)>;
277 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
278 resets = <&rctl STM32_RESET(APB1, 15U)>;
286 clocks = <&rcc STM32_CLOCK(APB1, 16U)>;
287 resets = <&rctl STM32_RESET(APB1, 16U)>;
295 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
[all …]
/Zephyr-latest/dts/arm/st/l4/
Dstm32l431.dtsi53 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
83 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
108 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
127 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
Dstm32l432.dtsi33 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
41 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
59 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
72 clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
80 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
Dstm32l471.dtsi51 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
69 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
81 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
102 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
110 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
132 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
154 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
176 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
[all …]

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