1/*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f0/stm32f031.dtsi>
8
9/ {
10
11	clocks {
12		clk_hsi48: clk-hsi48 {
13			#clock-cells = <0>;
14			compatible = "fixed-clock";
15			clock-frequency = <DT_FREQ_M(48)>;
16			status = "disabled";
17		};
18	};
19
20	soc {
21		compatible = "st,stm32f042", "st,stm32f0", "simple-bus";
22
23
24		usart2: serial@40004400 {
25			compatible = "st,stm32-usart", "st,stm32-uart";
26			reg = <0x40004400 0x400>;
27			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
28			resets = <&rctl STM32_RESET(APB1, 17U)>;
29			interrupts = <28 0>;
30			status = "disabled";
31		};
32
33		spi2: spi@40003800 {
34			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
35			#address-cells = <1>;
36			#size-cells = <0>;
37			reg = <0x40003800 0x400>;
38			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
39			interrupts = <26 3>;
40			status = "disabled";
41		};
42
43		can1: can@40006400 {
44			compatible = "st,stm32-bxcan";
45			reg = <0x40006400 0x400>;
46			interrupts = <30 0>;
47			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
48			status = "disabled";
49		};
50
51		timers15: timers@40014000 {
52			compatible = "st,stm32-timers";
53			reg = <0x40014000 0x400>;
54			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
55			resets = <&rctl STM32_RESET(APB2, 16U)>;
56			interrupts = <20 0>;
57			interrupt-names = "global";
58			st,prescaler = <0>;
59			status = "disabled";
60
61			pwm {
62				compatible = "st,stm32-pwm";
63				status = "disabled";
64				#pwm-cells = <3>;
65			};
66		};
67
68		usb: usb@40005c00 {
69			compatible = "st,stm32-usb";
70			reg = <0x40005c00 0x400>;
71			interrupts = <31 0>;
72			interrupt-names = "usb";
73			num-bidir-endpoints = <8>;
74			ram-size = <1024>;
75			phys = <&usb_fs_phy>;
76			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
77				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
78			status = "disabled";
79		};
80	};
81
82	usb_fs_phy: usbphy {
83		compatible = "usb-nop-xceiv";
84		#phy-cells = <0>;
85	};
86};
87