1/*
2 * Copyright (c) 2022 Liam Clark
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l4/stm32l4.dtsi>
8
9/ {
10
11	clocks {
12		clk_hsi48: clk-hsi48 {
13			#clock-cells = <0>;
14			compatible = "fixed-clock";
15			clock-frequency = <DT_FREQ_M(48)>;
16			status = "disabled";
17		};
18	};
19
20	soc {
21		compatible = "st,stm32l431", "st,stm32l4", "simple-bus";
22
23		pinctrl: pin-controller@48000000 {
24
25			gpiod: gpio@48000c00 {
26				compatible = "st,stm32-gpio";
27				reg = <0x48000c00 0x400>;
28				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
29				gpio-controller;
30				#gpio-cells = <2>;
31			};
32
33			gpioe: gpio@48001000 {
34				compatible = "st,stm32-gpio";
35				reg = <0x48001000 0x400>;
36				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
37				gpio-controller;
38				#gpio-cells = <2>;
39			};
40
41		};
42
43		rng: rng@50060800 {
44			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
45				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
46		};
47
48		i2c2: i2c@40005800 {
49			compatible = "st,stm32-i2c-v2";
50			#address-cells = <1>;
51			#size-cells = <0>;
52			reg = <0x40005800 0x400>;
53			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
54			clock-frequency = <I2C_BITRATE_STANDARD>;
55			interrupts = <33 0>, <34 0>;
56			interrupt-names = "event", "error";
57			status = "disabled";
58		};
59
60		spi2: spi@40003800 {
61			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
62			#address-cells = <1>;
63			#size-cells = <0>;
64			reg = <0x40003800 0x400>;
65			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
66			interrupts = <36 5>;
67			status = "disabled";
68		};
69
70		spi3: spi@40003c00 {
71			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
72			#address-cells = <1>;
73			#size-cells = <0>;
74			reg = <0x40003c00 0x400>;
75			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
76			interrupts = <51 5>;
77			status = "disabled";
78		};
79
80		usart3: serial@40004800 {
81			compatible = "st,stm32-usart", "st,stm32-uart";
82			reg = <0x40004800 0x400>;
83			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
84			resets = <&rctl STM32_RESET(APB1L, 18U)>;
85			interrupts = <39 0>;
86			status = "disabled";
87		};
88
89		timers7: timers@40001400 {
90			compatible = "st,stm32-timers";
91			reg = <0x40001400 0x400>;
92			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
93			resets = <&rctl STM32_RESET(APB1L, 5U)>;
94			interrupts = <55 0>;
95			interrupt-names = "global";
96			st,prescaler = <0>;
97			status = "disabled";
98
99			counter {
100				compatible = "st,stm32-counter";
101				status = "disabled";
102			};
103		};
104
105		can1: can@40006400 {
106			compatible = "st,stm32-bxcan";
107			reg = <0x40006400 0x400>;
108			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
109			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
110			interrupt-names = "TX", "RX0", "RX1", "SCE";
111			status = "disabled";
112		};
113
114		sdmmc1: sdmmc@40012800 {
115			compatible = "st,stm32-sdmmc";
116			reg = <0x40012800 0x400>;
117			clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
118				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
119			resets = <&rctl STM32_RESET(APB2, 10U)>;
120			interrupts = <49 0>;
121			status = "disabled";
122		};
123
124		dac1: dac@40007400 {
125			compatible = "st,stm32-dac";
126			reg = <0x40007400 0x400>;
127			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
128			#io-channel-cells = <1>;
129			status = "disabled";
130		};
131	};
132
133	smbus2: smbus2 {
134		compatible = "st,stm32-smbus";
135		#address-cells = <1>;
136		#size-cells = <0>;
137		i2c = <&i2c2>;
138		status = "disabled";
139	};
140};
141