Home
last modified time | relevance | path

Searched +full:0 +full:x10000 (Results 1 – 25 of 173) sorted by relevance

1234567

/Zephyr-latest/dts/arm/nxp/
Dnxp_s32z27x_rtu1_r52.dtsi12 /delete-node/ cpu@0;
22 reg = <0x7d900000 DT_SIZE_M(7)>;
27 reg = <0x76a00000 0x10000>;
35 reg = <0x76a10000 0x10000>;
43 reg = <0x76820000 0x10000>;
51 reg = <0x76830000 0x10000>;
59 reg = <0x76800000 0x10000>;
68 reg = <0x76810000 0x10000>;
77 reg = <0x76a20000 0x10000>;
86 reg = <0x76a30000 0x10000>;
[all …]
Dnxp_s32z27x_rtu0_r52.dtsi22 reg = <0x79900000 DT_SIZE_M(7)>;
27 reg = <0x76200000 0x10000>;
35 reg = <0x76210000 0x10000>;
43 reg = <0x76020000 0x10000>;
51 reg = <0x76030000 0x10000>;
59 reg = <0x76000000 0x10000>;
68 reg = <0x76010000 0x10000>;
77 reg = <0x76220000 0x10000>;
86 reg = <0x76230000 0x10000>;
95 reg = <0x76140000 0x10000>;
[all …]
Dnxp_s32z27x_r52.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
87 reg = <0x40030000 0x10000>,
88 <0x40200000 0x10000>,
89 <0x40210000 0x10000>,
90 <0x40220000 0x10000>,
91 <0x40260000 0x10000>,
92 <0x40270000 0x10000>,
93 <0x40830000 0x10000>,
[all …]
Dnxp_imx7d_m4.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
29 reg = <0x10000000 0xfff0000>;
35 reg = <0x80000000 0x60000000>;
40 reg = <0x1fff8000 DT_SIZE_K(32)>;
45 reg = <0x20000000 DT_SIZE_K(32)>;
50 reg = <0x00900000 DT_SIZE_K(128)>;
56 reg = <0x20200000 DT_SIZE_K(128)>;
59 /* OCRAM_S 0x20180000 is aliased at 0 */
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
32 reg = <0x40250000 0x10000>;
40 reg = <0x10000000 DT_SIZE_K(384)>;
46 reg = <0x10060000 DT_SIZE_K(640)>;
53 reg = <0x08000000 DT_SIZE_K(140)>;
58 reg = <0x08023000 DT_SIZE_K(4)>;
64 reg = <0x08024000 DT_SIZE_K(112)>;
73 ranges = <0x40310000 0x40310000 0x2024>;
[all …]
/Zephyr-latest/dts/arm64/fvp/
Dfvp-aemv8r.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
56 #clock-cells = <0>;
64 reg = <0xaf000000 0x10000>,
65 <0xaf100000 0x200000>;
73 reg = <0x9c090000 0x10000>;
82 reg = <0x9c0a0000 0x10000>;
91 reg = <0x9c0b0000 0x10000>;
100 reg = <0x9c0c0000 0x10000>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/
Dpsoc6_04.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x40000>;
41 reg = <0x14000000 0x0>;
49 reg = <0x8000000 0x20000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_03/
Dpsoc6_03.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x80000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x40000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
/Zephyr-latest/dts/arm64/rockchip/
Drk3399.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0x0 0x0>;
27 reg = <0x0 0x1>;
32 reg = <0x0 0x2>;
37 reg = <0x0 0x3>;
42 reg = <0x0 0x100>;
47 reg = <0x0 0x101>;
54 reg = <0xfee00000 0x10000>, /* GICD */
55 <0xfef00000 0xc0000>, /* GICR */
[all …]
Drk3568.dtsi23 #size-cells = <0>;
29 reg = <0x000>;
36 reg = <0x100>;
43 reg = <0x200>;
51 reg = <0x300>;
61 reg = <0xfd400000 0x10000>, /* GICD */
62 <0xfd460000 0xc0000>; /* GICR */
82 reg = <0xfe660000 0x10000>;
/Zephyr-latest/soc/espressif/common/
DKconfig.amp16 default 0x10000
22 default 0x10000
/Zephyr-latest/tests/drivers/flash_simulator/flash_sim_reboot/boards/
Dmps2_an385.overlay6 reg = <0x203F0000 0x10000>;
16 erase-value = <0xff>;
19 flash_sim0: flash_sim@0 {
21 reg = <0x00000000 0x10000>;
/Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/boards/
Dcolibri_imx7d_mcimx7d_m4.overlay20 /* use DDR_SYS area as mmio, 0x90000000 0x10000 */
21 reg = <0x90000000 0x10000>;
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_02/
Dpsoc6_02.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x200000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x100000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi17 #size-cells= <0>;
19 cpu@0 {
23 reg = <0x0>;
30 reg = <0x100>;
37 reg = <0x200>;
44 reg = <0x300>;
50 reg = <0x1d000000 0x10000>, /* GICD */
51 <0x1d060000 0x80000>; /* GICR */
60 reg = <0x1d040000 0x20000>;
76 reg = <0x10d12000 0x1000>;
[all …]
/Zephyr-latest/tests/drivers/build_all/i2c/boards/
Dqemu_cortex_m3.overlay13 #size-cells = <0>;
14 reg = <0x88888888 0x10000>;
22 #size-cells = <0>;
23 reg = <0x88898888 0x10000>;
32 #size-cells = <0>;
33 reg = <0x888A8888 0x100>;
/Zephyr-latest/boards/digilent/arty_a7/dts/
Darty_a7_arm_designstart.dtsi42 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
86 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
106 gpios = <&gpio0_2 0 GPIO_ACTIVE_HIGH>;
126 gpios = <&gpio1_2 0 GPIO_ACTIVE_HIGH>;
151 interrupts = <7 0>;
152 mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>;
159 reg = <0x40010000 0x10000>;
163 xlnx,all-inputs = <0x0>;
164 xlnx,all-outputs = <0x0>;
165 xlnx,dout-default = <0x0>;
[all …]
/Zephyr-latest/dts/bindings/ospi/
Dst,stm32-ospi.yaml9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
15 dmas = <&dma1 5 41 0x10000>;
34 pinctrl-0:
47 dmas = <&dma1 5 41 0x10000>;
51 - 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
53 - 0x10000: channel configuration (only for srce/dest data size, priority)
60 0 is a correct value.
64 dmas = <&dma1 5 41 0x10000>;
94 Specifies which port of the OCTOSPI IO Manager is used for the IO[3:0] pins.
/Zephyr-latest/boards/phytec/phyboard_pollux/
Dphyboard_pollux_mimx8ml8_m7.dts31 reg = <0x30860000 0x10000>;
33 clocks = <&ccm IMX_CCM_UART1_CLK 0x7c 24>;
34 pinctrl-0 = <&uart1_default>;
45 reg = <0x30880000 0x10000>;
47 clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>;
48 pinctrl-0 = <&uart3_default>;
62 pinctrl-0 = <&uart4_default>;
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_01/
Dpsoc6_01.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40250000 0x10000 >;
35 reg = <0x10000000 0x100000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x48000>;
55 reg = <0x40310000 0x20000>;
57 #size-cells = <0>;
62 reg = <0x40310000 0x4000>;
[all …]
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi18 #size-cells = <0>;
20 cpu@0 {
21 clock-frequency = <0>;
36 reg = <0>;
43 #address-cells = <0>;
50 clock-frequency = <0>;
72 #address-cells = <0>;
81 reg = <0x0 0x80000000 0x2 0x0>;
101 reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
107 reg = <0x0 0x1808000 0x0 0x8000>;
[all …]
/Zephyr-latest/boards/xen/xenvm/
Dxenvm_xenvm_gicv3.dts10 reg = <0x00 0x3001000 0x00 0x10000 0x00 0x3020000 0x00 0x1000000>;
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
Dmemory.h9 #define IRAM_RESERVE_HEADER_SPACE 0x400
11 #define IRAM_BASE 0x21170000
12 #define IRAM_SIZE 0x10000
14 #define SDRAM0_BASE 0x1a000000
15 #define SDRAM0_SIZE 0x800000
17 #define SDRAM1_BASE 0x1a800000
18 #define SDRAM1_SIZE 0x800000
21 #define MEM_RESET_TEXT_SIZE 0x2e0
22 #define MEM_RESET_LIT_SIZE 0x120
28 #define MEM_VECBASE_LIT_SIZE 0x178
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6e2bb3cfm.dtsi12 reg = <0x407e0000 0x10000>;
16 flash0: flash@0 {
18 reg = <0x0 DT_SIZE_K(256)>;
Dr7fa6m4af3cfb.dtsi12 reg = <0x407e0000 0x10000>;
16 flash0: flash@0 {
18 reg = <0x0 DT_SIZE_M(1)>;

1234567