Lines Matching +full:0 +full:x10000
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
87 reg = <0x40030000 0x10000>,
88 <0x40200000 0x10000>,
89 <0x40210000 0x10000>,
90 <0x40220000 0x10000>,
91 <0x40260000 0x10000>,
92 <0x40270000 0x10000>,
93 <0x40830000 0x10000>,
94 <0x41030000 0x10000>,
95 <0x41830000 0x10000>,
96 <0x42030000 0x10000>,
97 <0x42830000 0x10000>,
98 <0x44030000 0x10000>,
99 <0x440a0000 0x10000>;
106 reg = <0x47800000 0x10000>,
107 <0x47900000 0x80000>;
115 reg = <0x31780000 DT_SIZE_M(1)>;
120 reg = <0x35780000 DT_SIZE_M(1)>;
125 reg = <0x40170000 0x1000>;
132 reg = <0x40180000 0x1000>;
139 reg = <0x40190000 0x1000>;
146 reg = <0x40970000 0x1000>;
153 reg = <0x40980000 0x1000>;
160 reg = <0x40990000 0x1000>;
167 reg = <0x42170000 0x1000>;
174 reg = <0x42180000 0x1000>;
181 reg = <0x42190000 0x1000>;
188 reg = <0x42980000 0x1000>;
195 reg = <0x42990000 0x1000>;
202 reg = <0x429a0000 0x1000>;
209 reg = <0x40330000 0x1000>;
215 reg = <0x40520000 0x10000>;
221 reg = <0x40520010 0xb4>;
230 reg = <0x40521702 0x02>, <0x40520240 0x40>;
233 interrupts = <1 1>, <3 0>, <5 2>, <12 3>,
243 reg = <0x40521700 0x02>, <0x40520280 0x40>;
246 interrupts = <0 7>;
255 reg = <0x40521716 0x02>, <0x405204c0 0x40>;
260 gpio-reserved-ranges = <0 10>;
266 reg = <0x40d20000 0x10000>;
272 reg = <0x40d20010 0xb4>;
281 reg = <0x40d21700 0x02>, <0x40d20280 0x40>;
284 interrupts = <3 0>, <5 1>;
288 gpio-reserved-ranges = <0 15>;
294 reg = <0x40d21706 0x02>, <0x40d202c0 0x40>;
304 reg = <0x40d21704 0x02>, <0x40d20300 0x40>;
314 reg = <0x40d2170a 0x02>, <0x40d20340 0x40>;
324 reg = <0x40d21708 0x02>, <0x40d20380 0x40>;
327 interrupts = <0 2>, <1 3>, <4 4>,
337 reg = <0x41d20000 0x10000>;
341 reg = <0x42520000 0x10000>;
347 reg = <0x42520010 0xb4>;
356 reg = <0x42521708 0x02>, <0x42520380 0x40>;
361 gpio-reserved-ranges = <0 12>;
367 reg = <0x4252170e 0x02>, <0x425203c0 0x40>;
370 interrupts = <11 0>, <13 1>;
379 reg = <0x4252170c 0x02>, <0x42520400 0x40>;
391 reg = <0x42521712 0x02>, <0x42520440 0x40>;
404 reg = <0x42521710 0x02>, <0x42520480 0x40>;
414 reg = <0x42d20000 0x10000>;
420 reg = <0x42d20010 0xb4>;
429 reg = <0x42d21710 0x02>, <0x42d20480 0x40>;
432 interrupts = <1 0>, <3 1>, <5 2>, <7 3>;
436 gpio-reserved-ranges = <0 2>;
442 reg = <0x42d21716 0x02>, <0x42d204c0 0x40>;
445 interrupts = <0 4>, <2 5>, <5 6>, <6 7>;
455 reg = <0x40130000 0x10000>;
460 #size-cells = <0>;
466 reg = <0x40140000 0x10000>;
471 #size-cells = <0>;
477 reg = <0x40930000 0x10000>;
482 #size-cells = <0>;
488 reg = <0x40940000 0x10000>;
493 #size-cells = <0>;
499 reg = <0x40950000 0x10000>;
504 #size-cells = <0>;
510 reg = <0x42130000 0x10000>;
515 #size-cells = <0>;
521 reg = <0x42140000 0x10000>;
526 #size-cells = <0>;
532 reg = <0x42150000 0x10000>;
537 #size-cells = <0>;
543 reg = <0x42930000 0x10000>;
548 #size-cells = <0>;
554 reg = <0x42940000 0x10000>;
559 #size-cells = <0>;
565 reg = <0x40340000 0x10000>;
569 #size-cells = <0>;
575 reg = <0x76070000 0x10000>;
583 reg = <0x76090000 0x10000>;
591 reg = <0x76270000 0x10000>;
599 reg = <0x76290000 0x10000>;
607 reg = <0x76870000 0x10000>;
615 reg = <0x76890000 0x10000>;
623 reg = <0x76a70000 0x10000>;
631 reg = <0x76a90000 0x10000>;
638 reg = <0x74000000 0x1000000>;
645 reg = <0x74b60000 0x1c44>;
648 #size-cells = <0>;
653 reg = <0x74b00000 0x10000>;
659 reg = <0x74bc0000 0x10000>;
665 reg = <0x74bd0000 0x10000>;
671 reg = <0x74be0000 0x10000>;
677 reg = <0x74bf0000 0x10000>;
683 reg = <0x74c00000 0x10000>;
689 reg = <0x74c10000 0x10000>;
695 reg = <0x74c20000 0x10000>;
702 reg = <0x4741b000 0x1000>,
703 <0x47423000 0x1000>,
704 <0x47425000 0x1000>,
705 <0x47427000 0x1000>;
709 <GIC_SPI 225 IRQ_TYPE_LEVEL 0xb0>;
716 reg = <0x4751b000 0x1000>,
717 <0x47523000 0x1000>,
718 <0x47525000 0x1000>,
719 <0x47527000 0x1000>;
723 <GIC_SPI 227 IRQ_TYPE_LEVEL 0xb0>;
730 reg = <0x449a0000 0x4000>;
731 clk-source = <0>;
745 reg = <0x449b0000 0x4000>;
746 clk-source = <0>;
760 clk-source = <0>;
761 reg = <0x449c0000 0x4000>;
775 clk-source = <0>;
776 reg = <0x449d0000 0x4000>;
790 clk-source = <0>;
791 reg = <0x449e0000 0x4000>;
805 clk-source = <0>;
806 reg = <0x449f0000 0x4000>;
820 clk-source = <0>;
821 reg = <0x44ba0000 0x4000>;
835 clk-source = <0>;
836 reg = <0x44bb0000 0x4000>;
850 clk-source = <0>;
851 reg = <0x44bc0000 0x4000>;
865 clk-source = <0>;
866 reg = <0x44bd0000 0x4000>;
880 clk-source = <0>;
881 reg = <0x44be0000 0x4000>;
895 clk-source = <0>;
896 reg = <0x44bf0000 0x4000>;
910 clk-source = <0>;
911 reg = <0x44da0000 0x4000>;
925 clk-source = <0>;
926 reg = <0x44db0000 0x4000>;
940 clk-source = <0>;
941 reg = <0x44dc0000 0x4000>;
955 clk-source = <0>;
956 reg = <0x44dd0000 0x4000>;
970 clk-source = <0>;
971 reg = <0x44de0000 0x4000>;
985 clk-source = <0>;
986 reg = <0x44df0000 0x4000>;
1000 clk-source = <0>;
1001 reg = <0x44fa0000 0x4000>;
1015 clk-source = <0>;
1016 reg = <0x44fb0000 0x4000>;
1030 clk-source = <0>;
1031 reg = <0x44fc0000 0x4000>;
1045 clk-source = <0>;
1046 reg = <0x44fd0000 0x4000>;
1060 clk-source = <0>;
1061 reg = <0x44fe0000 0x4000>;
1075 clk-source = <0>;
1076 reg = <0x44ff0000 0x4000>;
1090 reg = <0x402C0000 0x1000>;
1100 reg = <0x402e0000 0x1000>;
1110 reg = <0x409d0000 0x10000>;
1112 #size-cells = <0>;
1121 reg = <0x421d0000 0x10000>;
1123 #size-cells = <0>;
1133 reg = <0x405d0000 0x10000>, <0x405a0000 0x10000>, <0x405b0000 0x100000>;
1178 reg = <0x40dd0000 0x10000>, <0x40da0000 0x10000>;
1207 reg = <0x425d0000 0x10000>, <0x425a0000 0x10000>;
1236 reg = <0x42dd0000 0x10000>, <0x42da0000 0x10000>;