Lines Matching +full:0 +full:x10000

16 		#size-cells = <0>;
18 		cpu@0 {
21 			reg = <0>;
29 			reg = <0x10000000 0xfff0000>;
35 			reg = <0x80000000 0x60000000>;
40 			reg = <0x1fff8000 DT_SIZE_K(32)>;
45 			reg = <0x20000000 DT_SIZE_K(32)>;
50 			reg = <0x00900000 DT_SIZE_K(128)>;
56 			reg = <0x20200000 DT_SIZE_K(128)>;
59 		/* OCRAM_S 0x20180000 is aliased at 0 */
60 		ocram_s_code: code@0 {
62 			reg = <0x00000000 DT_SIZE_K(32)>;
68 			reg = <0x00180000 DT_SIZE_K(32)>;
73 			reg = <0x30200000 0x10000>;
74 			interrupts = <64 0>, <65 0>;
86 			reg = <0x30210000 0x10000>;
87 			interrupts = <66 0>, <67 0>;
99 			reg = <0x30220000 0x10000>;
100 			interrupts = <68 0>, <69 0>;
112 			reg = <0x30230000 0x10000>;
113 			interrupts = <70 0>, <71 0>;
125 			reg = <0x30240000 0x10000>;
126 			interrupts = <72 0>, <73 0>;
138 			reg = <0x30250000 0x10000>;
139 			interrupts = <74 0>, <75 0>;
151 			reg = <0x30260000 0x10000>;
152 			interrupts = <76 0>, <77 0>;
167 			reg = <0x30860000 0x10000>;
178 			reg = <0x30890000 0x10000>;
189 			reg = <0x30880000 0x10000>;
200 			reg = <0x30a60000 0x10000>;
211 			reg = <0x30a70000 0x10000>;
222 			reg = <0x30a80000 0x10000>;
233 			reg = <0x30a90000 0x10000>;
244 			reg = <0x30ab0000 0x4000>;
245 			interrupts = <97 0>;
253 			reg = <0x30330000 DT_SIZE_K(64)>;
265 			#size-cells = <0>;
266 			reg = <0x30a20000 0x10000>;
267 			interrupts = <35 0>;
279 			#size-cells = <0>;
280 			reg = <0x30a30000 0x10000>;
281 			interrupts = <36 0>;
293 			#size-cells = <0>;
294 			reg = <0x30a40000 0x10000>;
295 			interrupts = <37 0>;
307 			#size-cells = <0>;
308 			reg = <0x30a50000 0x10000>;
309 			interrupts = <38 0>;
319 			reg = <0x30660000 0x10000>;
320 			interrupts = <81 0>;
321 			prescaler = <0>;
332 			reg = <0x30670000 0x10000>;
333 			interrupts = <82 0>;
334 			prescaler = <0>;
345 			reg = <0x30680000 0x10000>;
346 			interrupts = <83 0>;
347 			prescaler = <0>;
358 			reg = <0x30690000 0x10000>;
359 			interrupts = <84 0>;
360 			prescaler = <0>;