1/* 2 * Copyright (c) 2017, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv7-m.dtsi> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/rdc/imx_rdc.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-m4"; 21 reg = <0>; 22 }; 23 }; 24 25 soc { 26 27 ddr_code: code@10000000 { 28 compatible = "nxp,imx-code-bus"; 29 reg = <0x10000000 0xfff0000>; 30 }; 31 32 ddr_sys: memory@80000000 { 33 device_type = "memory"; 34 compatible = "nxp,imx-sys-bus"; 35 reg = <0x80000000 0x60000000>; 36 }; 37 38 tcml_code: code@1fff8000 { 39 compatible = "nxp,imx-itcm"; 40 reg = <0x1fff8000 DT_SIZE_K(32)>; 41 }; 42 43 tcmu_sys: memory@20000000 { 44 compatible = "nxp,imx-dtcm"; 45 reg = <0x20000000 DT_SIZE_K(32)>; 46 }; 47 48 ocram_code: code@900000 { 49 compatible = "nxp,imx-code-bus"; 50 reg = <0x00900000 DT_SIZE_K(128)>; 51 }; 52 53 ocram_sys: memory@20200000 { 54 device_type = "memory"; 55 compatible = "nxp,imx-sys-bus"; 56 reg = <0x20200000 DT_SIZE_K(128)>; 57 }; 58 59 /* OCRAM_S 0x20180000 is aliased at 0 */ 60 ocram_s_code: code@0 { 61 compatible = "nxp,imx-code-bus"; 62 reg = <0x00000000 DT_SIZE_K(32)>; 63 }; 64 65 ocram_s_sys: memory@180000 { 66 device_type = "memory"; 67 compatible = "nxp,imx-sys-bus"; 68 reg = <0x00180000 DT_SIZE_K(32)>; 69 }; 70 71 gpio1: gpio@30200000 { 72 compatible = "nxp,imx-gpio"; 73 reg = <0x30200000 0x10000>; 74 interrupts = <64 0>, <65 0>; 75 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 76 RDC_DOMAIN_PERM_RW)|\ 77 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 78 RDC_DOMAIN_PERM_RW))>; 79 gpio-controller; 80 #gpio-cells = <2>; 81 status = "disabled"; 82 }; 83 84 gpio2: gpio@30210000 { 85 compatible = "nxp,imx-gpio"; 86 reg = <0x30210000 0x10000>; 87 interrupts = <66 0>, <67 0>; 88 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 89 RDC_DOMAIN_PERM_RW)|\ 90 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 91 RDC_DOMAIN_PERM_RW))>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 status = "disabled"; 95 }; 96 97 gpio3: gpio@30220000 { 98 compatible = "nxp,imx-gpio"; 99 reg = <0x30220000 0x10000>; 100 interrupts = <68 0>, <69 0>; 101 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 102 RDC_DOMAIN_PERM_RW)|\ 103 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 104 RDC_DOMAIN_PERM_RW))>; 105 gpio-controller; 106 #gpio-cells = <2>; 107 status = "disabled"; 108 }; 109 110 gpio4: gpio@30230000 { 111 compatible = "nxp,imx-gpio"; 112 reg = <0x30230000 0x10000>; 113 interrupts = <70 0>, <71 0>; 114 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 115 RDC_DOMAIN_PERM_RW)|\ 116 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 117 RDC_DOMAIN_PERM_RW))>; 118 gpio-controller; 119 #gpio-cells = <2>; 120 status = "disabled"; 121 }; 122 123 gpio5: gpio@30240000 { 124 compatible = "nxp,imx-gpio"; 125 reg = <0x30240000 0x10000>; 126 interrupts = <72 0>, <73 0>; 127 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 128 RDC_DOMAIN_PERM_RW)|\ 129 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 130 RDC_DOMAIN_PERM_RW))>; 131 gpio-controller; 132 #gpio-cells = <2>; 133 status = "disabled"; 134 }; 135 136 gpio6: gpio@30250000 { 137 compatible = "nxp,imx-gpio"; 138 reg = <0x30250000 0x10000>; 139 interrupts = <74 0>, <75 0>; 140 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 141 RDC_DOMAIN_PERM_RW)|\ 142 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 143 RDC_DOMAIN_PERM_RW))>; 144 gpio-controller; 145 #gpio-cells = <2>; 146 status = "disabled"; 147 }; 148 149 gpio7: gpio@30260000 { 150 compatible = "nxp,imx-gpio"; 151 reg = <0x30260000 0x10000>; 152 interrupts = <76 0>, <77 0>; 153 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 154 RDC_DOMAIN_PERM_RW)|\ 155 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 156 RDC_DOMAIN_PERM_RW))>; 157 gpio-controller; 158 #gpio-cells = <2>; 159 status = "disabled"; 160 }; 161 162 /* For now only uart2 is supported and 163 * tested with the serial driver 164 */ 165 uart1: uart@30860000 { 166 compatible = "nxp,imx-uart"; 167 reg = <0x30860000 0x10000>; 168 interrupts = <26 3>; 169 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 170 RDC_DOMAIN_PERM_RW)|\ 171 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 172 RDC_DOMAIN_PERM_RW))>; 173 status = "disabled"; 174 }; 175 176 uart2: uart@30890000 { 177 compatible = "nxp,imx-uart"; 178 reg = <0x30890000 0x10000>; 179 interrupts = <27 3>; 180 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 181 RDC_DOMAIN_PERM_RW)|\ 182 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 183 RDC_DOMAIN_PERM_RW))>; 184 status = "disabled"; 185 }; 186 187 uart3: uart@30880000 { 188 compatible = "nxp,imx-uart"; 189 reg = <0x30880000 0x10000>; 190 interrupts = <28 3>; 191 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 192 RDC_DOMAIN_PERM_RW)|\ 193 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 194 RDC_DOMAIN_PERM_RW))>; 195 status = "disabled"; 196 }; 197 198 uart4: uart@30a60000 { 199 compatible = "nxp,imx-uart"; 200 reg = <0x30a60000 0x10000>; 201 interrupts = <29 3>; 202 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 203 RDC_DOMAIN_PERM_RW)|\ 204 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 205 RDC_DOMAIN_PERM_RW))>; 206 status = "disabled"; 207 }; 208 209 uart5: uart@30a70000 { 210 compatible = "nxp,imx-uart"; 211 reg = <0x30a70000 0x10000>; 212 interrupts = <30 3>; 213 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 214 RDC_DOMAIN_PERM_RW)|\ 215 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 216 RDC_DOMAIN_PERM_RW))>; 217 status = "disabled"; 218 }; 219 220 uart6: uart@30a80000 { 221 compatible = "nxp,imx-uart"; 222 reg = <0x30a80000 0x10000>; 223 interrupts = <16 3>; 224 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 225 RDC_DOMAIN_PERM_RW)|\ 226 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 227 RDC_DOMAIN_PERM_RW))>; 228 status = "disabled"; 229 }; 230 231 uart7: uart@30a90000 { 232 compatible = "nxp,imx-uart"; 233 reg = <0x30a90000 0x10000>; 234 interrupts = <126 3>; 235 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 236 RDC_DOMAIN_PERM_RW)|\ 237 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 238 RDC_DOMAIN_PERM_RW))>; 239 status = "disabled"; 240 }; 241 242 mub:mu@30ab0000 { 243 compatible = "nxp,imx-mu"; 244 reg = <0x30ab0000 0x4000>; 245 interrupts = <97 0>; 246 rdc = <RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 247 RDC_DOMAIN_PERM_RW)>; 248 status = "disabled"; 249 }; 250 251 iomuxc: iomuxc@30330000 { 252 compatible = "nxp,imx-iomuxc"; 253 reg = <0x30330000 DT_SIZE_K(64)>; 254 status = "okay"; 255 pinctrl: pinctrl { 256 status = "okay"; 257 compatible = "nxp,imx7d-pinctrl"; 258 }; 259 }; 260 261 i2c1: i2c@30a20000 { 262 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 263 clock-frequency = <I2C_BITRATE_STANDARD>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 reg = <0x30a20000 0x10000>; 267 interrupts = <35 0>; 268 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 269 RDC_DOMAIN_PERM_RW)|\ 270 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 271 RDC_DOMAIN_PERM_RW))>; 272 status = "disabled"; 273 }; 274 275 i2c2: i2c@30a30000 { 276 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 277 clock-frequency = <I2C_BITRATE_STANDARD>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x30a30000 0x10000>; 281 interrupts = <36 0>; 282 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 283 RDC_DOMAIN_PERM_RW)|\ 284 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 285 RDC_DOMAIN_PERM_RW))>; 286 status = "disabled"; 287 }; 288 289 i2c3: i2c@30a40000 { 290 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 291 clock-frequency = <I2C_BITRATE_STANDARD>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0x30a40000 0x10000>; 295 interrupts = <37 0>; 296 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 297 RDC_DOMAIN_PERM_RW)|\ 298 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 299 RDC_DOMAIN_PERM_RW))>; 300 status = "disabled"; 301 }; 302 303 i2c4: i2c@30a50000 { 304 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 305 clock-frequency = <I2C_BITRATE_STANDARD>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x30a50000 0x10000>; 309 interrupts = <38 0>; 310 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 311 RDC_DOMAIN_PERM_RW)|\ 312 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 313 RDC_DOMAIN_PERM_RW))>; 314 status = "disabled"; 315 }; 316 317 pwm1: pwm@30660000 { 318 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 319 reg = <0x30660000 0x10000>; 320 interrupts = <81 0>; 321 prescaler = <0>; 322 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 323 RDC_DOMAIN_PERM_RW)|\ 324 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 325 RDC_DOMAIN_PERM_RW))>; 326 status = "disabled"; 327 #pwm-cells = <2>; 328 }; 329 330 pwm2: pwm@30670000 { 331 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 332 reg = <0x30670000 0x10000>; 333 interrupts = <82 0>; 334 prescaler = <0>; 335 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 336 RDC_DOMAIN_PERM_RW)|\ 337 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 338 RDC_DOMAIN_PERM_RW))>; 339 status = "disabled"; 340 #pwm-cells = <2>; 341 }; 342 343 pwm3: pwm@30680000 { 344 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 345 reg = <0x30680000 0x10000>; 346 interrupts = <83 0>; 347 prescaler = <0>; 348 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 349 RDC_DOMAIN_PERM_RW)|\ 350 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 351 RDC_DOMAIN_PERM_RW))>; 352 status = "disabled"; 353 #pwm-cells = <2>; 354 }; 355 356 pwm4: pwm@30690000 { 357 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 358 reg = <0x30690000 0x10000>; 359 interrupts = <84 0>; 360 prescaler = <0>; 361 rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ 362 RDC_DOMAIN_PERM_RW)|\ 363 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 364 RDC_DOMAIN_PERM_RW))>; 365 status = "disabled"; 366 #pwm-cells = <2>; 367 }; 368 }; 369}; 370 371&nvic { 372 arm,num-irq-priority-bits = <4>; 373}; 374 375 376/* 377 * GPIO pinmux options. These options define the pinmux settings 378 * for GPIO ports on the package, so that the GPIO driver can 379 * select GPIO mux options during GPIO configuration. 380 */ 381 382&gpio1 { 383 pinmux = <&mx7d_pad_lpsr_gpio1_io00__gpio1_io0>, 384 <&mx7d_pad_lpsr_gpio1_io01__gpio1_io1>, 385 <&mx7d_pad_lpsr_gpio1_io02__gpio1_io2>, 386 <&mx7d_pad_lpsr_gpio1_io03__gpio1_io3>, 387 <&mx7d_pad_lpsr_gpio1_io04__gpio1_io4>, 388 <&mx7d_pad_lpsr_gpio1_io05__gpio1_io5>, 389 <&mx7d_pad_lpsr_gpio1_io06__gpio1_io6>, 390 <&mx7d_pad_lpsr_gpio1_io07__gpio1_io7>, 391 <&mx7d_pad_gpio1_io08__gpio1_io8>, 392 <&mx7d_pad_gpio1_io09__gpio1_io9>, 393 <&mx7d_pad_gpio1_io10__gpio1_io10>, 394 <&mx7d_pad_gpio1_io11__gpio1_io11>, 395 <&mx7d_pad_gpio1_io12__gpio1_io12>, 396 <&mx7d_pad_gpio1_io13__gpio1_io13>, 397 <&mx7d_pad_gpio1_io14__gpio1_io14>, 398 <&mx7d_pad_gpio1_io15__gpio1_io15>; 399}; 400 401&gpio2 { 402 pinmux = <&mx7d_pad_epdc_data00__gpio2_io0>, 403 <&mx7d_pad_epdc_data01__gpio2_io1>, 404 <&mx7d_pad_epdc_data02__gpio2_io2>, 405 <&mx7d_pad_epdc_data03__gpio2_io3>, 406 <&mx7d_pad_epdc_data04__gpio2_io4>, 407 <&mx7d_pad_epdc_data05__gpio2_io5>, 408 <&mx7d_pad_epdc_data06__gpio2_io6>, 409 <&mx7d_pad_epdc_data07__gpio2_io7>, 410 <&mx7d_pad_epdc_data08__gpio2_io8>, 411 <&mx7d_pad_epdc_data09__gpio2_io9>, 412 <&mx7d_pad_epdc_data10__gpio2_io10>, 413 <&mx7d_pad_epdc_data11__gpio2_io11>, 414 <&mx7d_pad_epdc_data12__gpio2_io12>, 415 <&mx7d_pad_epdc_data13__gpio2_io13>, 416 <&mx7d_pad_epdc_data14__gpio2_io14>, 417 <&mx7d_pad_epdc_data15__gpio2_io15>, 418 <&mx7d_pad_epdc_sdclk__gpio2_io16>, 419 <&mx7d_pad_epdc_sdle__gpio2_io17>, 420 <&mx7d_pad_epdc_sdoe__gpio2_io18>, 421 <&mx7d_pad_epdc_sdshr__gpio2_io19>, 422 <&mx7d_pad_epdc_sdce0__gpio2_io20>, 423 <&mx7d_pad_epdc_sdce1__gpio2_io21>, 424 <&mx7d_pad_epdc_sdce2__gpio2_io22>, 425 <&mx7d_pad_epdc_sdce3__gpio2_io23>, 426 <&mx7d_pad_epdc_gdclk__gpio2_io24>, 427 <&mx7d_pad_epdc_gdoe__gpio2_io25>, 428 <&mx7d_pad_epdc_gdrl__gpio2_io26>, 429 <&mx7d_pad_epdc_gdsp__gpio2_io27>, 430 <&mx7d_pad_epdc_bdr0__gpio2_io28>, 431 <&mx7d_pad_epdc_bdr1__gpio2_io29>, 432 <&mx7d_pad_epdc_pwr_com__gpio2_io30>, 433 <&mx7d_pad_epdc_pwr_stat__gpio2_io31>; 434}; 435 436&gpio3 { 437 pinmux = <&mx7d_pad_lcd_clk__gpio3_io0>, 438 <&mx7d_pad_lcd_enable__gpio3_io1>, 439 <&mx7d_pad_lcd_hsync__gpio3_io2>, 440 <&mx7d_pad_lcd_vsync__gpio3_io3>, 441 <&mx7d_pad_lcd_reset__gpio3_io4>, 442 <&mx7d_pad_lcd_data00__gpio3_io5>, 443 <&mx7d_pad_lcd_data01__gpio3_io6>, 444 <&mx7d_pad_lcd_data02__gpio3_io7>, 445 <&mx7d_pad_lcd_data03__gpio3_io8>, 446 <&mx7d_pad_lcd_data04__gpio3_io9>, 447 <&mx7d_pad_lcd_data05__gpio3_io10>, 448 <&mx7d_pad_lcd_data06__gpio3_io11>, 449 <&mx7d_pad_lcd_data07__gpio3_io12>, 450 <&mx7d_pad_lcd_data08__gpio3_io13>, 451 <&mx7d_pad_lcd_data09__gpio3_io14>, 452 <&mx7d_pad_lcd_data10__gpio3_io15>, 453 <&mx7d_pad_lcd_data11__gpio3_io16>, 454 <&mx7d_pad_lcd_data12__gpio3_io17>, 455 <&mx7d_pad_lcd_data13__gpio3_io18>, 456 <&mx7d_pad_lcd_data14__gpio3_io19>, 457 <&mx7d_pad_lcd_data15__gpio3_io20>, 458 <&mx7d_pad_lcd_data16__gpio3_io21>, 459 <&mx7d_pad_lcd_data17__gpio3_io22>, 460 <&mx7d_pad_lcd_data18__gpio3_io23>, 461 <&mx7d_pad_lcd_data19__gpio3_io24>, 462 <&mx7d_pad_lcd_data20__gpio3_io25>, 463 <&mx7d_pad_lcd_data21__gpio3_io26>, 464 <&mx7d_pad_lcd_data22__gpio3_io27>, 465 <&mx7d_pad_lcd_data23__gpio3_io28>; 466}; 467 468&gpio4 { 469 pinmux = <&mx7d_pad_uart1_rx_data__gpio4_io0>, 470 <&mx7d_pad_uart1_tx_data__gpio4_io1>, 471 <&mx7d_pad_uart2_rx_data__gpio4_io2>, 472 <&mx7d_pad_uart2_tx_data__gpio4_io3>, 473 <&mx7d_pad_uart3_rx_data__gpio4_io4>, 474 <&mx7d_pad_uart3_tx_data__gpio4_io5>, 475 <&mx7d_pad_uart3_rts_b__gpio4_io6>, 476 <&mx7d_pad_uart3_cts_b__gpio4_io7>, 477 <&mx7d_pad_i2c1_scl__gpio4_io8>, 478 <&mx7d_pad_i2c1_sda__gpio4_io9>, 479 <&mx7d_pad_i2c2_scl__gpio4_io10>, 480 <&mx7d_pad_i2c2_sda__gpio4_io11>, 481 <&mx7d_pad_i2c3_scl__gpio4_io12>, 482 <&mx7d_pad_i2c3_sda__gpio4_io13>, 483 <&mx7d_pad_i2c4_scl__gpio4_io14>, 484 <&mx7d_pad_i2c4_sda__gpio4_io15>, 485 <&mx7d_pad_ecspi1_sclk__gpio4_io16>, 486 <&mx7d_pad_ecspi1_mosi__gpio4_io17>, 487 <&mx7d_pad_ecspi1_miso__gpio4_io18>, 488 <&mx7d_pad_ecspi1_ss0__gpio4_io19>, 489 <&mx7d_pad_ecspi2_sclk__gpio4_io20>, 490 <&mx7d_pad_ecspi2_mosi__gpio4_io21>, 491 <&mx7d_pad_ecspi2_miso__gpio4_io22>, 492 <&mx7d_pad_ecspi2_ss0__gpio4_io23>; 493}; 494 495&gpio5 { 496 pinmux = <&mx7d_pad_sd1_cd_b__gpio5_io0>, 497 <&mx7d_pad_sd1_wp__gpio5_io1>, 498 <&mx7d_pad_sd1_reset_b__gpio5_io2>, 499 <&mx7d_pad_sd1_clk__gpio5_io3>, 500 <&mx7d_pad_sd1_cmd__gpio5_io4>, 501 <&mx7d_pad_sd1_data0__gpio5_io5>, 502 <&mx7d_pad_sd1_data1__gpio5_io6>, 503 <&mx7d_pad_sd1_data2__gpio5_io7>, 504 <&mx7d_pad_sd1_data3__gpio5_io8>, 505 <&mx7d_pad_sd2_cd_b__gpio5_io9>, 506 <&mx7d_pad_sd2_wp__gpio5_io10>, 507 <&mx7d_pad_sd2_reset_b__gpio5_io11>, 508 <&mx7d_pad_sd2_clk__gpio5_io12>, 509 <&mx7d_pad_sd2_cmd__gpio5_io13>, 510 <&mx7d_pad_sd2_data0__gpio5_io14>, 511 <&mx7d_pad_sd2_data1__gpio5_io15>, 512 <&mx7d_pad_sd2_data2__gpio5_io16>, 513 <&mx7d_pad_sd2_data3__gpio5_io17>; 514}; 515 516&gpio6 { 517 pinmux = <&mx7d_pad_sd3_clk__gpio6_io0>, 518 <&mx7d_pad_sd3_cmd__gpio6_io1>, 519 <&mx7d_pad_sd3_data0__gpio6_io2>, 520 <&mx7d_pad_sd3_data1__gpio6_io3>, 521 <&mx7d_pad_sd3_data2__gpio6_io4>, 522 <&mx7d_pad_sd3_data3__gpio6_io5>, 523 <&mx7d_pad_sd3_data4__gpio6_io6>, 524 <&mx7d_pad_sd3_data5__gpio6_io7>, 525 <&mx7d_pad_sd3_data6__gpio6_io8>, 526 <&mx7d_pad_sd3_data7__gpio6_io9>, 527 <&mx7d_pad_sd3_strobe__gpio6_io10>, 528 <&mx7d_pad_sd3_reset_b__gpio6_io11>, 529 <&mx7d_pad_sai1_rx_data__gpio6_io12>, 530 <&mx7d_pad_sai1_tx_bclk__gpio6_io13>, 531 <&mx7d_pad_sai1_tx_sync__gpio6_io14>, 532 <&mx7d_pad_sai1_tx_data__gpio6_io15>, 533 <&mx7d_pad_sai1_rx_sync__gpio6_io16>, 534 <&mx7d_pad_sai1_rx_bclk__gpio6_io17>, 535 <&mx7d_pad_sai1_mclk__gpio6_io18>, 536 <&mx7d_pad_sai2_tx_sync__gpio6_io19>, 537 <&mx7d_pad_sai2_tx_bclk__gpio6_io20>, 538 <&mx7d_pad_sai2_rx_data__gpio6_io21>, 539 <&mx7d_pad_sai2_tx_data__gpio6_io22>; 540}; 541 542&gpio7 { 543 pinmux = <&mx7d_pad_enet1_rgmii_rd0__gpio7_io0>, 544 <&mx7d_pad_enet1_rgmii_rd1__gpio7_io1>, 545 <&mx7d_pad_enet1_rgmii_rd2__gpio7_io2>, 546 <&mx7d_pad_enet1_rgmii_rd3__gpio7_io3>, 547 <&mx7d_pad_enet1_rgmii_rx_ctl__gpio7_io4>, 548 <&mx7d_pad_enet1_rgmii_rxc__gpio7_io5>, 549 <&mx7d_pad_enet1_rgmii_td0__gpio7_io6>, 550 <&mx7d_pad_enet1_rgmii_td1__gpio7_io7>, 551 <&mx7d_pad_enet1_rgmii_td2__gpio7_io8>, 552 <&mx7d_pad_enet1_rgmii_td3__gpio7_io9>, 553 <&mx7d_pad_enet1_rgmii_tx_ctl__gpio7_io10>, 554 <&mx7d_pad_enet1_rgmii_txc__gpio7_io11>, 555 <&mx7d_pad_enet1_tx_clk__gpio7_io12>, 556 <&mx7d_pad_enet1_rx_clk__gpio7_io13>, 557 <&mx7d_pad_enet1_crs__gpio7_io14>, 558 <&mx7d_pad_enet1_col__gpio7_io15>; 559}; 560
