1/*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/nxp/nxp_s32z27x_r52.dtsi>
8
9/ {
10
11	cpus {
12		/delete-node/ cpu@0;
13		/delete-node/ cpu@1;
14		/delete-node/ cpu@2;
15		/delete-node/ cpu@3;
16	};
17
18	soc {
19		/* Accessing code RAM over AXIF - a read-only flash memory bus */
20		cram1: memory@7d900000 {
21			compatible = "mmio-sram";
22			reg = <0x7d900000 DT_SIZE_M(7)>;
23		};
24
25		stm0: stm@76a00000 {
26			compatible = "nxp,s32-sys-timer";
27			reg = <0x76a00000 0x10000>;
28			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
29			clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
30			status = "disabled";
31		};
32
33		stm1: stm@76a10000 {
34			compatible = "nxp,s32-sys-timer";
35			reg = <0x76a10000 0x10000>;
36			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
37			clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
38			status = "disabled";
39		};
40
41		stm2: stm@76820000 {
42			compatible = "nxp,s32-sys-timer";
43			reg = <0x76820000 0x10000>;
44			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
45			clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
46			status = "disabled";
47		};
48
49		stm3: stm@76830000 {
50			compatible = "nxp,s32-sys-timer";
51			reg = <0x76830000 0x10000>;
52			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
53			clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
54			status = "disabled";
55		};
56
57		swt0: watchdog@76800000 {
58			compatible = "nxp,s32-swt";
59			reg = <0x76800000 0x10000>;
60			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
61			clocks = <&clock NXP_S32_FIRC_CLK>;
62			service-mode = "fixed";
63			status = "disabled";
64		};
65
66		swt1: watchdog@76810000 {
67			compatible = "nxp,s32-swt";
68			reg = <0x76810000 0x10000>;
69			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
70			clocks = <&clock NXP_S32_FIRC_CLK>;
71			service-mode = "fixed";
72			status = "disabled";
73		};
74
75		swt2: watchdog@76a20000 {
76			compatible = "nxp,s32-swt";
77			reg = <0x76a20000 0x10000>;
78			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
79			clocks = <&clock NXP_S32_FIRC_CLK>;
80			service-mode = "fixed";
81			status = "disabled";
82		};
83
84		swt3: watchdog@76a30000 {
85			compatible = "nxp,s32-swt";
86			reg = <0x76a30000 0x10000>;
87			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
88			clocks = <&clock NXP_S32_FIRC_CLK>;
89			service-mode = "fixed";
90			status = "disabled";
91		};
92
93		swt4: watchdog@76940000 {
94			compatible = "nxp,s32-swt";
95			reg = <0x76940000 0x10000>;
96			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
97			clocks = <&clock NXP_S32_FIRC_CLK>;
98			service-mode = "fixed";
99			status = "disabled";
100		};
101
102		pit0: pit@76950000 {
103			compatible = "nxp,pit";
104			reg = <0x76950000 0x10000>;
105			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
106			clocks = <&clock NXP_S32_P1_REG_INTF_CLK>;
107			max-load-value = <0x00ffffff>;
108			status = "disabled";
109			#address-cells = <1>;
110			#size-cells = <0>;
111
112			pit0_channel0: pit0_channel@0 {
113				compatible = "nxp,pit-channel";
114				reg = <0>;
115				status = "disabled";
116			};
117
118			pit0_channel1: pit0_channel@1 {
119				compatible = "nxp,pit-channel";
120				reg = <1>;
121				status = "disabled";
122			};
123
124			pit0_channel2: pit0_channel@2 {
125				compatible = "nxp,pit-channel";
126				reg = <2>;
127				status = "disabled";
128			};
129
130			pit0_channel3: pit0_channel@3 {
131				compatible = "nxp,pit-channel";
132				reg = <3>;
133				status = "disabled";
134			};
135
136			pit0_channel4: pit0_channel@4 {
137				compatible = "nxp,pit-channel";
138				reg = <4>;
139				status = "disabled";
140			};
141
142			pit0_channel5: pit0_channel@5 {
143				compatible = "nxp,pit-channel";
144				reg = <5>;
145				status = "disabled";
146			};
147		};
148	};
149};
150