1/*
2 * Copyright 2020 NXP
3 * Copyright 2022 HNU-ESNL
4 * Copyright 2022 openEuler SIG-Zephyr
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include <mem.h>
10#include <arm64/armv8-a.dtsi>
11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12
13
14/ {
15	#address-cells = <1>;
16	#size-cells = <1>;
17
18	compatible = "rockchip,rk3568";
19	interrupt-parent = <&gic>;
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu@000 {
26			device_type = "cpu";
27			compatible = "arm,cortex-a55";
28			enable-method = "psci";
29			reg = <0x000>;
30		};
31
32		cpu@100 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a55";
35			enable-method = "psci";
36			reg = <0x100>;
37		};
38
39		cpu@200 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a55";
42			enable-method = "psci";
43			reg = <0x200>;
44
45		};
46
47		cpu@300 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a55";
50			enable-method = "psci";
51			reg = <0x300>;
52		};
53	};
54
55	gic: interrupt-controller@fd400000 {
56		#address-cells = <1>;
57		compatible = "arm,gic-v3","arm,gic";
58		#interrupt-cells = <4>;
59		interrupt-controller;
60
61		reg = <0xfd400000 0x10000>, /* GICD */
62		      <0xfd460000 0xc0000>; /* GICR */
63		status = "okay";
64	};
65
66	psci {
67		compatible = "arm,psci-0.2", "arm,psci";
68		method = "smc";
69	};
70
71	timer {
72		compatible = "arm,armv8-timer";
73		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
74			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
75			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
76			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
77		interrupt-parent = <&gic>;
78	};
79
80	uart2: serial@fe660000 {
81		compatible = "rockchip,rk3568-uart", "ns16550";
82		reg = <0xfe660000 0x10000>;
83		interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
84		clock-frequency = <12000000>;
85		reg-shift = <2>;
86		status = "disabled";
87	};
88
89};
90