1 /*
2  * Copyright (c) 2023 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
7 #define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
8 
9 #define IRAM_RESERVE_HEADER_SPACE	0x400
10 
11 #define IRAM_BASE	0x21170000
12 #define IRAM_SIZE	0x10000
13 
14 #define SDRAM0_BASE	0x1a000000
15 #define SDRAM0_SIZE	0x800000
16 
17 #define SDRAM1_BASE	0x1a800000
18 #define SDRAM1_SIZE	0x800000
19 
20 /* The reset vector address in SRAM and its size */
21 #define MEM_RESET_TEXT_SIZE			0x2e0
22 #define MEM_RESET_LIT_SIZE			0x120
23 
24 /* This is the base address of all the vectors defined in IRAM */
25 #define XCHAL_VECBASE_RESET_PADDR_IRAM \
26 		(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
27 
28 #define MEM_VECBASE_LIT_SIZE			0x178
29 
30 /*
31  * EXCEPTIONS and VECTORS
32  */
33 #define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x21170000
34 
35 /* Vector and literal sizes */
36 #define MEM_VECT_LIT_SIZE			0x4
37 #define MEM_VECT_TEXT_SIZE			0x1C
38 #define MEM_VECT_SIZE				(MEM_VECT_TEXT_SIZE +\
39 						 MEM_VECT_LIT_SIZE)
40 
41 /* The addresses of the vectors.
42  * Only the mem_error vector continues to point to its ROM address.
43  */
44 #define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
45 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
46 
47 #define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
48 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
49 
50 #define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
51 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
52 
53 #define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
54 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
55 
56 #define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
57 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
58 
59 #define XCHAL_USER_VECTOR_PADDR_IRAM \
60 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
61 
62 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
63 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
64 
65 /* Location for the intList section which is later used to construct the
66  * Interrupt Descriptor Table (IDT). This is a bogus address as this
67  * section will be stripped off in the final image.
68  */
69 #define IDT_BASE	(IRAM_BASE + IRAM_SIZE)
70 
71 /* size of the Interrupt Descriptor Table (IDT) */
72 #define IDT_SIZE	0x2000
73 
74 /* physical DSP addresses */
75 #define IRAM_BASE	0x21170000
76 #define IRAM_SIZE	0x10000
77 
78 #define DRAM0_BASE	0x21180000
79 #define DRAM0_SIZE	0x10000
80 
81 #define SDRAM0_BASE	0x1a000000
82 #define SDRAM0_SIZE	0x800000
83 
84 #define SDRAM1_BASE	0x1a800000
85 #define SDRAM1_SIZE	0x800000
86 
87 #define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x2DA20000
88 #define MU_BASE		XSHAL_MU13_SIDEB_BYPASS_PADDR
89 
90 #define EDMA2_BASE	0x2D810000
91 #define EDMA2_SIZE	0x10000
92 
93 #define SAI_5_BASE	0x29890000
94 #define SAI_5_SIZE	0x00010000
95 #define SAI_6_BASE	0x2DA90000
96 #define SAI_6_SIZE	0x00010000
97 #define SAI_7_BASE	0x2DAA0000
98 #define SAI_7_SIZE	0x00010000
99 
100 #define UUID_ENTRY_ELF_BASE	0x1FFFA000
101 #define UUID_ENTRY_ELF_SIZE	0x6000
102 
103 #define LOG_ENTRY_ELF_BASE	0x20000000
104 #define LOG_ENTRY_ELF_SIZE	0x2000000
105 
106 #define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
107 #define EXT_MANIFEST_ELF_SIZE	0x2000000
108 
109 /*
110  * The Heap and Stack on i.MX8 are organized like this :-
111  *
112  * +--------------------------------------------------------------------------+
113  * | Offset              | Region         |  Size                             |
114  * +---------------------+----------------+-----------------------------------+
115  * | SDRAM_BASE          | RO Data        |  SOF_DATA_SIZE                    |
116  * |                     | Data           |                                   |
117  * |                     | BSS            |                                   |
118  * +---------------------+----------------+-----------------------------------+
119  * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
120  * +---------------------+----------------+-----------------------------------+
121  * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
122  * +---------------------+----------------+-----------------------------------+
123  * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
124  * +---------------------+----------------+-----------------------------------+
125  * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
126  * +---------------------+----------------+-----------------------------------+
127  * | SOF_STACK_BASE      |                |                                   |
128  * +---------------------+----------------+-----------------------------------+
129  */
130 
131 #define SRAM_OUTBOX_BASE	SDRAM1_BASE
132 #define SRAM_OUTBOX_SIZE	0x1000
133 #define SRAM_OUTBOX_OFFSET	0
134 
135 #define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
136 #define SRAM_INBOX_SIZE		0x1000
137 #define SRAM_INBOX_OFFSET	SRAM_OUTBOX_SIZE
138 
139 #define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
140 #define SRAM_DEBUG_SIZE		0x2800
141 #define SRAM_DEBUG_OFFSET	(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
142 
143 #define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
144 #define SRAM_EXCEPT_SIZE	0x800
145 #define SRAM_EXCEPT_OFFSET	(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
146 
147 #define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
148 #define SRAM_STREAM_SIZE	0x1000
149 #define SRAM_STREAM_OFFSET	(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
150 
151 #define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
152 #define SRAM_TRACE_SIZE		0x1000
153 #define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
154 
155 #define SOF_MAILBOX_SIZE	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
156 				+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
157 				+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
158 
159 #endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
160