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/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <8000000>;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
30 #clock-cells = <0>;
31 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
46 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dsystem_clocks.dtsi13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <48000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <8000000>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <96000000>;
37 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2l1xxxxfp.dtsi16 xtal: clock-main-osc {
17 compatible = "renesas,ra-cgc-external-clock";
18 clock-frequency = <DT_FREQ_M(20)>;
19 #clock-cells = <0>;
23 hoco: clock-hoco {
24 compatible = "fixed-clock";
25 clock-frequency = <DT_FREQ_M(48)>;
26 #clock-cells = <0>;
29 moco: clock-moco {
30 compatible = "fixed-clock";
[all …]
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_clk.dtsi9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
27 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32mg21.dtsi11 #include <dt-bindings/clock/silabs/xg21-clock.h>
23 #clock-cells = <0>;
24 compatible = "fixed-factor-clock";
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
32 clock-div = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
39 clock-div = <2>;
42 #clock-cells = <0>;
[all …]
Defr32xg23.dtsi11 #include <dt-bindings/clock/silabs/xg23-clock.h>
23 #clock-cells = <0>;
24 compatible = "fixed-factor-clock";
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
33 #clock-cells = <0>;
34 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
42 clock-div = <1>;
[all …]
Defr32mg24.dtsi11 #include <dt-bindings/clock/silabs/xg24-clock.h>
23 #clock-cells = <0>;
24 compatible = "fixed-factor-clock";
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
33 #clock-cells = <0>;
34 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
42 clock-div = <1>;
[all …]
Defr32bg2x.dtsi22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
31 clock-div = <1>;
34 #clock-cells = <0>;
35 compatible = "fixed-factor-clock";
38 clock-div = <2>;
41 #clock-cells = <0>;
42 compatible = "fixed-factor-clock";
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi23 clock-names = "GCLK", "MCLK";
25 atmel,assigned-clock-names = "GCLK";
37 clock-names = "GCLK", "MCLK";
39 atmel,assigned-clock-names = "GCLK";
51 clock-names = "GCLK", "MCLK";
53 atmel,assigned-clock-names = "GCLK";
65 clock-names = "GCLK", "MCLK";
67 atmel,assigned-clock-names = "GCLK";
73 clock-names = "GCLK", "MCLK";
75 atmel,assigned-clock-names = "GCLK";
[all …]
Dsamd20.dtsi23 clock-names = "GCLK", "PM";
25 atmel,assigned-clock-names = "GCLK";
34 clock-names = "GCLK", "PM";
36 atmel,assigned-clock-names = "GCLK";
45 clock-names = "GCLK", "PM";
47 atmel,assigned-clock-names = "GCLK";
56 clock-names = "GCLK", "PM";
58 atmel,assigned-clock-names = "GCLK";
63 clock-names = "GCLK", "PM";
65 atmel,assigned-clock-names = "GCLK";
[all …]
Dsamd21.dtsi43 clock-names = "GCLK", "PM";
45 atmel,assigned-clock-names = "GCLK";
54 clock-names = "GCLK", "PM";
56 atmel,assigned-clock-names = "GCLK";
68 clock-names = "GCLK", "PM";
70 atmel,assigned-clock-names = "GCLK";
82 clock-names = "GCLK", "PM";
84 atmel,assigned-clock-names = "GCLK";
96 clock-names = "GCLK", "PM";
98 atmel,assigned-clock-names = "GCLK";
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
48 compatible = "raspberrypi,pico-clock";
50 clock-names = "pll_sys";
51 clock-frequency = <125000000>;
52 #clock-cells = <0>;
57 compatible = "raspberrypi,pico-clock";
59 clock-names = "pll_sys";
60 clock-frequency = <125000000>;
61 #clock-cells = <0>;
65 compatible = "raspberrypi,pico-clock";
[all …]
Drp2350.dtsi9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
44 compatible = "raspberrypi,pico-clock";
46 clock-names = "pll_sys";
47 clock-frequency = <150000000>;
48 #clock-cells = <0>;
53 compatible = "raspberrypi,pico-clock";
55 clock-names = "pll_sys";
56 clock-frequency = <150000000>;
57 #clock-cells = <0>;
61 compatible = "raspberrypi,pico-clock";
[all …]
/Zephyr-latest/dts/arm/silabs/xg29/
Dxg29.dtsi11 #include <dt-bindings/clock/silabs/xg29-clock.h>
23 #clock-cells = <0>;
24 compatible = "fixed-factor-clock";
29 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
41 #clock-cells = <0>;
42 compatible = "fixed-factor-clock";
45 clock-div = <1>;
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts92 /* System clock configuration */
95 clock-frequency = <100000000>;
99 clock-div = <1>;
103 /* CM4 core clock = 100MHz
104 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
107 clock-div = <1>;
110 /* CM0+ core clock = 50MHz
111 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
114 clock-div = <2>;
117 /* PERI core clock = 100MHz
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4w1ad2cng.dtsi7 #include <zephyr/dt-bindings/clock/ra_clock.h>
64 xtal: clock-main-osc {
65 compatible = "renesas,ra-cgc-external-clock";
66 clock-frequency = <DT_FREQ_M(8)>;
67 #clock-cells = <0>;
71 hoco: clock-hoco {
72 compatible = "fixed-clock";
73 clock-frequency = <DT_FREQ_M(48)>;
74 #clock-cells = <0>;
77 moco: clock-moco {
[all …]
Dr7fa4e10x.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
74 xtal: clock-main-osc {
75 compatible = "renesas,ra-cgc-external-clock";
76 clock-frequency = <DT_FREQ_M(24)>;
77 #clock-cells = <0>;
81 hoco: clock-hoco {
82 compatible = "fixed-clock";
83 clock-frequency = <DT_FREQ_M(20)>;
84 #clock-cells = <0>;
87 moco: clock-moco {
[all …]
Dr7fa4e2b93cfm.dtsi7 #include <zephyr/dt-bindings/clock/ra_clock.h>
76 clock-names = "opclk", "ramclk";
87 clock-names = "dllclk";
102 xtal: clock-main-osc {
103 compatible = "renesas,ra-cgc-external-clock";
104 clock-frequency = <DT_FREQ_M(20)>;
105 #clock-cells = <0>;
109 hoco: clock-hoco {
110 compatible = "fixed-clock";
111 clock-frequency = <DT_FREQ_M(20)>;
[all …]
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dcy8ckit_062s2_ai.dts53 clock-frequency = <100000000>;
57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
62 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
65 clock-div = <1>;
68 /* CM0+ core clock = 50MHz
69 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
72 clock-div = <2>;
75 /* PERI core clock = 100MHz
76 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
24 clock-frequency = <DT_FREQ_M(48)>;
25 #clock-cells = <0>;
28 moco: clock-moco {
[all …]
Dr7fa8m1xh.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
24 clock-frequency = <DT_FREQ_M(48)>;
25 #clock-cells = <0>;
28 moco: clock-moco {
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi7 #include <zephyr/dt-bindings/clock/ra_clock.h>
54 xtal: clock-main-osc {
55 compatible = "renesas,ra-cgc-external-clock";
56 clock-frequency = <DT_FREQ_M(12)>;
57 #clock-cells = <0>;
61 hoco: clock-hoco {
62 compatible = "fixed-clock";
63 clock-frequency = <DT_FREQ_M(20)>;
64 #clock-cells = <0>;
67 moco: clock-moco {
[all …]
Dr7fa6e2bx.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
54 clock-names = "opclk", "ramclk";
65 clock-names = "dllclk";
100 xtal: clock-main-osc {
101 compatible = "renesas,ra-cgc-external-clock";
102 clock-frequency = <DT_FREQ_M(20)>;
103 #clock-cells = <0>;
107 hoco: clock-hoco {
108 compatible = "fixed-clock";
109 clock-frequency = <DT_FREQ_M(20)>;
[all …]
/Zephyr-latest/drivers/timer/
DKconfig.nrf_xrtc14 System clock source is initiated but does not wait for clock readiness.
15 When this option is picked, system clock may not be ready when code relying
22 System clock source initialization waits until clock is available. In some
23 systems, clock initially runs from less accurate source which has faster
24 startup time and then seamlessly switches to the target clock source when
25 it is ready. When this option is picked, system clock is available after
26 system clock driver initialization but it may be less accurate. Option is
27 equivalent to waiting for stability if clock source does not have
33 System clock source initialization waits until clock is stable. When this
34 option is picked, system clock is available and stable after system clock
/Zephyr-latest/dts/arm/adi/max32/
Dmax32xxx.dtsi9 #include <zephyr/dt-bindings/clock/adi_max32_clock.h>
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <DT_FREQ_M(100)>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <DT_FREQ_M(60)>;
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <DT_FREQ_K(8)>;
[all …]

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