| /hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/src/ |
| D | stm32f4xx_ll_fmc.c | 246 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
247 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
248 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
249 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
250 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
251 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
252 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
254 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); in FMC_NORSRAM_Init()
256 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
257 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32f4xx_ll_fsmc.c | 227 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
228 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); in FSMC_NORSRAM_Init()
229 assert_param(IS_FSMC_MUX(Init->DataAddressMux)); in FSMC_NORSRAM_Init()
230 assert_param(IS_FSMC_MEMORY(Init->MemoryType)); in FSMC_NORSRAM_Init()
231 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FSMC_NORSRAM_Init()
232 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); in FSMC_NORSRAM_Init()
233 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FSMC_NORSRAM_Init()
235 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); in FSMC_NORSRAM_Init()
237 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FSMC_NORSRAM_Init()
238 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); in FSMC_NORSRAM_Init()
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| /hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/ |
| D | stm32f7xx_ll_fmc.c | 197 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
198 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
199 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
200 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
201 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
202 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
203 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
204 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
205 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
206 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32f7xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
221 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
355 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
356 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
357 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
552 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
553 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
554 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
555 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
556 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
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| /hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/src/ |
| D | stm32h7xx_ll_fmc.c | 197 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
198 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
199 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
200 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
201 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
202 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
203 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
204 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
205 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
206 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32h7xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
231 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
367 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
368 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
369 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
564 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
565 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
566 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
567 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
568 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/ |
| D | stm32h5xx_ll_fmc.c | 198 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
199 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
200 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
201 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
202 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
203 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
204 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
205 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
206 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
207 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32h5xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
248 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
376 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
377 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
378 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
573 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
574 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
575 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
576 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
577 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/src/ |
| D | stm32f1xx_ll_fsmc.c | 215 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
216 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); in FSMC_NORSRAM_Init()
217 assert_param(IS_FSMC_MUX(Init->DataAddressMux)); in FSMC_NORSRAM_Init()
218 assert_param(IS_FSMC_MEMORY(Init->MemoryType)); in FSMC_NORSRAM_Init()
219 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FSMC_NORSRAM_Init()
220 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); in FSMC_NORSRAM_Init()
221 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FSMC_NORSRAM_Init()
222 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); in FSMC_NORSRAM_Init()
223 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FSMC_NORSRAM_Init()
224 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); in FSMC_NORSRAM_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/src/ |
| D | stm32f2xx_ll_fsmc.c | 203 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
204 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); in FSMC_NORSRAM_Init()
205 assert_param(IS_FSMC_MUX(Init->DataAddressMux)); in FSMC_NORSRAM_Init()
206 assert_param(IS_FSMC_MEMORY(Init->MemoryType)); in FSMC_NORSRAM_Init()
207 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FSMC_NORSRAM_Init()
208 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); in FSMC_NORSRAM_Init()
209 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FSMC_NORSRAM_Init()
210 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); in FSMC_NORSRAM_Init()
211 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FSMC_NORSRAM_Init()
212 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); in FSMC_NORSRAM_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/src/ |
| D | stm32f3xx_ll_fmc.c | 208 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
209 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
210 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
211 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
212 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
213 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
214 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
215 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); in FMC_NORSRAM_Init()
216 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
217 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/ |
| D | stm32u5xx_ll_fmc.c | 181 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
182 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
183 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
184 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
185 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
186 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
187 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
188 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
189 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
190 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32u5xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
246 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
341 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
342 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
343 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
538 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
539 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
540 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
541 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
542 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/ |
| D | stm32g4xx_ll_fmc.c | 185 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
186 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
187 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
188 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
189 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
190 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
191 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
192 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
193 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
194 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32g4xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
235 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
339 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
340 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
341 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
536 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
537 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
538 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
539 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
540 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/src/ |
| D | stm32l5xx_ll_fmc.c | 180 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
181 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
182 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
183 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
184 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
185 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
186 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
187 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
188 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
189 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32l5xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
227 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
322 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
323 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
324 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
519 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
520 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
521 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
522 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
523 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/src/ |
| D | stm32l4xx_ll_fmc.c | 198 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
199 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
200 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
201 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
202 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
203 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
204 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
205 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
206 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
207 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
[all …]
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| D | stm32l4xx_hal_rtc.c | 254 assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); in HAL_RTC_Init()
255 assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); in HAL_RTC_Init()
256 assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); in HAL_RTC_Init()
257 assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); in HAL_RTC_Init()
258 assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); in HAL_RTC_Init()
259 assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); in HAL_RTC_Init()
260 assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); in HAL_RTC_Init()
261 assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); in HAL_RTC_Init()
263 assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); in HAL_RTC_Init()
267 assert_param(IS_RTC_BINARY_MODE(hrtc->Init.BinMode)); in HAL_RTC_Init()
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| D | stm32l4xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
221 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
328 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
329 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
330 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
525 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
526 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
527 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
528 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
529 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32c0xx/drivers/src/ |
| D | stm32c0xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
227 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
299 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
300 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
301 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
496 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
497 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
498 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
499 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
500 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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| /hal_stm32-3.5.0/stm32cube/stm32g0xx/drivers/src/ |
| D | stm32g0xx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
227 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
331 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
332 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
333 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
528 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
529 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
530 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
531 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
532 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
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| /hal_stm32-3.5.0/stm32cube/stm32wlxx/drivers/src/ |
| D | stm32wlxx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
227 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
287 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
288 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
289 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
484 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
485 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
486 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
487 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
488 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
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| /hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/ |
| D | stm32wbaxx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
235 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
304 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
305 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
306 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
501 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
502 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
503 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
504 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
505 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
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| /hal_stm32-3.5.0/stm32cube/stm32wbxx/drivers/src/ |
| D | stm32wbxx_ll_tim.c | 27 #define assert_param(expr) ((void)0U) macro
227 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_DeInit()
291 assert_param(IS_TIM_INSTANCE(TIMx)); in LL_TIM_Init()
292 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); in LL_TIM_Init()
293 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); in LL_TIM_Init()
488 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); in LL_TIM_ENCODER_Init()
489 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); in LL_TIM_ENCODER_Init()
490 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); in LL_TIM_ENCODER_Init()
491 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); in LL_TIM_ENCODER_Init()
492 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); in LL_TIM_ENCODER_Init()
[all …]
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