1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2017 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories and SDRAM memories. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Interface with synchronous DRAM (SDRAM) memories
50 (+) Independent Chip Select control for each memory bank
51 (+) Independent configuration for each memory bank
52
53 @endverbatim
54 ******************************************************************************
55 */
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32f7xx_hal.h"
59
60 /** @addtogroup STM32F7xx_HAL_Driver
61 * @{
62 */
63 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
64
65 /** @defgroup FMC_LL FMC Low Layer
66 * @brief FMC driver modules
67 * @{
68 */
69
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72
73 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
74 * @{
75 */
76
77 /* ----------------------- FMC registers bit mask --------------------------- */
78
79 /* --- BCR Register ---*/
80 /* BCR register clear mask */
81
82 /* --- BTR Register ---*/
83 /* BTR register clear mask */
84 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\
85 FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
86 FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\
87 FMC_BTR1_ACCMOD))
88
89 /* --- BWTR Register ---*/
90 /* BWTR register clear mask */
91 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\
92 FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
93 FMC_BWTR1_ACCMOD))
94
95 /* --- PCR Register ---*/
96 /* PCR register clear mask */
97 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
98 FMC_PCR_PTYP | FMC_PCR_PWID | \
99 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
100 FMC_PCR_TAR | FMC_PCR_ECCPS))
101 /* --- PMEM Register ---*/
102 /* PMEM register clear mask */
103 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 |\
104 FMC_PMEM_MEMHOLD3 | FMC_PMEM_MEMHIZ3))
105
106 /* --- PATT Register ---*/
107 /* PATT register clear mask */
108 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 |\
109 FMC_PATT_ATTHOLD3 | FMC_PATT_ATTHIZ3))
110
111
112 /* --- SDCR Register ---*/
113 /* SDCR register clear mask */
114 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \
115 FMC_SDCR1_MWID | FMC_SDCR1_NB | \
116 FMC_SDCR1_CAS | FMC_SDCR1_WP | \
117 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
118 FMC_SDCR1_RPIPE))
119
120 /* --- SDTR Register ---*/
121 /* SDTR register clear mask */
122 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \
123 FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \
124 FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
125 FMC_SDTR1_TRCD))
126
127 /**
128 * @}
129 */
130
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /* Exported functions --------------------------------------------------------*/
135
136 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
137 * @{
138 */
139
140
141 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
142 * @brief NORSRAM Controller functions
143 *
144 @verbatim
145 ==============================================================================
146 ##### How to use NORSRAM device driver #####
147 ==============================================================================
148
149 [..]
150 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
151 to run the NORSRAM external devices.
152
153 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
154 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
155 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
156 (+) FMC NORSRAM bank extended timing configuration using the function
157 FMC_NORSRAM_Extended_Timing_Init()
158 (+) FMC NORSRAM bank enable/disable write operation using the functions
159 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
160
161 @endverbatim
162 * @{
163 */
164
165 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
166 * @brief Initialization and Configuration functions
167 *
168 @verbatim
169 ==============================================================================
170 ##### Initialization and de_initialization functions #####
171 ==============================================================================
172 [..]
173 This section provides functions allowing to:
174 (+) Initialize and configure the FMC NORSRAM interface
175 (+) De-initialize the FMC NORSRAM interface
176 (+) Configure the FMC clock and associated GPIOs
177
178 @endverbatim
179 * @{
180 */
181
182 /**
183 * @brief Initialize the FMC_NORSRAM device according to the specified
184 * control parameters in the FMC_NORSRAM_InitTypeDef
185 * @param Device Pointer to NORSRAM device instance
186 * @param Init Pointer to NORSRAM Initialization structure
187 * @retval HAL status
188 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)189 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
190 FMC_NORSRAM_InitTypeDef *Init)
191 {
192 uint32_t flashaccess;
193 uint32_t btcr_reg;
194 uint32_t mask;
195
196 /* Check the parameters */
197 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
198 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
199 assert_param(IS_FMC_MUX(Init->DataAddressMux));
200 assert_param(IS_FMC_MEMORY(Init->MemoryType));
201 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
202 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
203 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
204 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
205 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
206 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
207 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
208 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
209 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
210 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
211 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
212 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
213
214 /* Disable NORSRAM Device */
215 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
216
217 /* Set NORSRAM device control parameters */
218 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
219 {
220 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
221 }
222 else
223 {
224 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
225 }
226
227 btcr_reg = (flashaccess | \
228 Init->DataAddressMux | \
229 Init->MemoryType | \
230 Init->MemoryDataWidth | \
231 Init->BurstAccessMode | \
232 Init->WaitSignalPolarity | \
233 Init->WaitSignalActive | \
234 Init->WriteOperation | \
235 Init->WaitSignal | \
236 Init->ExtendedMode | \
237 Init->AsynchronousWait | \
238 Init->WriteBurst);
239
240 btcr_reg |= Init->ContinuousClock;
241 btcr_reg |= Init->WriteFifo;
242 btcr_reg |= Init->PageSize;
243
244 mask = (FMC_BCR1_MBKEN |
245 FMC_BCR1_MUXEN |
246 FMC_BCR1_MTYP |
247 FMC_BCR1_MWID |
248 FMC_BCR1_FACCEN |
249 FMC_BCR1_BURSTEN |
250 FMC_BCR1_WAITPOL |
251 FMC_BCR1_WAITCFG |
252 FMC_BCR1_WREN |
253 FMC_BCR1_WAITEN |
254 FMC_BCR1_EXTMOD |
255 FMC_BCR1_ASYNCWAIT |
256 FMC_BCR1_CBURSTRW);
257
258 mask |= FMC_BCR1_CCLKEN;
259 mask |= FMC_BCR1_WFDIS;
260 mask |= FMC_BCR1_CPSIZE;
261
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
263
264 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
265 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
266 {
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
268 }
269
270 if (Init->NSBank != FMC_NORSRAM_BANK1)
271 {
272 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
273 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
274 }
275
276 return HAL_OK;
277 }
278
279 /**
280 * @brief DeInitialize the FMC_NORSRAM peripheral
281 * @param Device Pointer to NORSRAM device instance
282 * @param ExDevice Pointer to NORSRAM extended mode device instance
283 * @param Bank NORSRAM bank number
284 * @retval HAL status
285 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)286 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
287 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
288 {
289 /* Check the parameters */
290 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
291 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
292 assert_param(IS_FMC_NORSRAM_BANK(Bank));
293
294 /* Disable the FMC_NORSRAM device */
295 __FMC_NORSRAM_DISABLE(Device, Bank);
296
297 /* De-initialize the FMC_NORSRAM device */
298 /* FMC_NORSRAM_BANK1 */
299 if (Bank == FMC_NORSRAM_BANK1)
300 {
301 Device->BTCR[Bank] = 0x000030DBU;
302 }
303 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
304 else
305 {
306 Device->BTCR[Bank] = 0x000030D2U;
307 }
308
309 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
310 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
311
312 return HAL_OK;
313 }
314
315 /**
316 * @brief Initialize the FMC_NORSRAM Timing according to the specified
317 * parameters in the FMC_NORSRAM_TimingTypeDef
318 * @param Device Pointer to NORSRAM device instance
319 * @param Timing Pointer to NORSRAM Timing structure
320 * @param Bank NORSRAM bank number
321 * @retval HAL status
322 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)323 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
324 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
325 {
326 uint32_t tmpr;
327
328 /* Check the parameters */
329 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
330 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
331 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
332 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
333 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
334 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
335 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
336 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
337 assert_param(IS_FMC_NORSRAM_BANK(Bank));
338
339 /* Set FMC_NORSRAM device timing parameters */
340 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
341 ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) |
342 ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) |
343 ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) |
344 (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) |
345 (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) |
346 (Timing->AccessMode)));
347
348 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
349 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
350 {
351 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
352 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
353 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
354 }
355
356 return HAL_OK;
357 }
358
359 /**
360 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
361 * parameters in the FMC_NORSRAM_TimingTypeDef
362 * @param Device Pointer to NORSRAM device instance
363 * @param Timing Pointer to NORSRAM Timing structure
364 * @param Bank NORSRAM bank number
365 * @param ExtendedMode FMC Extended Mode
366 * This parameter can be one of the following values:
367 * @arg FMC_EXTENDED_MODE_DISABLE
368 * @arg FMC_EXTENDED_MODE_ENABLE
369 * @retval HAL status
370 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)371 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
372 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
373 uint32_t ExtendedMode)
374 {
375 /* Check the parameters */
376 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
377
378 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
379 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
380 {
381 /* Check the parameters */
382 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
383 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
384 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
385 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
386 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
387 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
388 assert_param(IS_FMC_NORSRAM_BANK(Bank));
389
390 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
391 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
392 ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) |
393 ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) |
394 Timing->AccessMode |
395 ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
396 }
397 else
398 {
399 Device->BWTR[Bank] = 0x0FFFFFFFU;
400 }
401
402 return HAL_OK;
403 }
404 /**
405 * @}
406 */
407
408 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
409 * @brief management functions
410 *
411 @verbatim
412 ==============================================================================
413 ##### FMC_NORSRAM Control functions #####
414 ==============================================================================
415 [..]
416 This subsection provides a set of functions allowing to control dynamically
417 the FMC NORSRAM interface.
418
419 @endverbatim
420 * @{
421 */
422
423 /**
424 * @brief Enables dynamically FMC_NORSRAM write operation.
425 * @param Device Pointer to NORSRAM device instance
426 * @param Bank NORSRAM bank number
427 * @retval HAL status
428 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)429 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
430 {
431 /* Check the parameters */
432 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
433 assert_param(IS_FMC_NORSRAM_BANK(Bank));
434
435 /* Enable write operation */
436 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
437
438 return HAL_OK;
439 }
440
441 /**
442 * @brief Disables dynamically FMC_NORSRAM write operation.
443 * @param Device Pointer to NORSRAM device instance
444 * @param Bank NORSRAM bank number
445 * @retval HAL status
446 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)447 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
448 {
449 /* Check the parameters */
450 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
451 assert_param(IS_FMC_NORSRAM_BANK(Bank));
452
453 /* Disable write operation */
454 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
455
456 return HAL_OK;
457 }
458
459 /**
460 * @}
461 */
462
463 /**
464 * @}
465 */
466
467
468 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
469 * @brief NAND Controller functions
470 *
471 @verbatim
472 ==============================================================================
473 ##### How to use NAND device driver #####
474 ==============================================================================
475 [..]
476 This driver contains a set of APIs to interface with the FMC NAND banks in order
477 to run the NAND external devices.
478
479 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
480 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
481 (+) FMC NAND bank common space timing configuration using the function
482 FMC_NAND_CommonSpace_Timing_Init()
483 (+) FMC NAND bank attribute space timing configuration using the function
484 FMC_NAND_AttributeSpace_Timing_Init()
485 (+) FMC NAND bank enable/disable ECC correction feature using the functions
486 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
487 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
488
489 @endverbatim
490 * @{
491 */
492
493 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
494 * @brief Initialization and Configuration functions
495 *
496 @verbatim
497 ==============================================================================
498 ##### Initialization and de_initialization functions #####
499 ==============================================================================
500 [..]
501 This section provides functions allowing to:
502 (+) Initialize and configure the FMC NAND interface
503 (+) De-initialize the FMC NAND interface
504 (+) Configure the FMC clock and associated GPIOs
505
506 @endverbatim
507 * @{
508 */
509
510 /**
511 * @brief Initializes the FMC_NAND device according to the specified
512 * control parameters in the FMC_NAND_HandleTypeDef
513 * @param Device Pointer to NAND device instance
514 * @param Init Pointer to NAND Initialization structure
515 * @retval HAL status
516 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)517 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
518 {
519 /* Check the parameters */
520 assert_param(IS_FMC_NAND_DEVICE(Device));
521 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
522 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
523 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
524 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
525 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
526 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
527 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
528
529 /* NAND bank 3 registers configuration */
530 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
531 FMC_PCR_MEMORY_TYPE_NAND |
532 Init->MemoryDataWidth |
533 Init->EccComputation |
534 Init->ECCPageSize |
535 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
536 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
537
538 return HAL_OK;
539 }
540
541 /**
542 * @brief Initializes the FMC_NAND Common space Timing according to the specified
543 * parameters in the FMC_NAND_PCC_TimingTypeDef
544 * @param Device Pointer to NAND device instance
545 * @param Timing Pointer to NAND timing structure
546 * @param Bank NAND bank number
547 * @retval HAL status
548 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)549 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
550 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
551 {
552 /* Check the parameters */
553 assert_param(IS_FMC_NAND_DEVICE(Device));
554 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
555 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
556 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
557 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
558 assert_param(IS_FMC_NAND_BANK(Bank));
559
560 /* Prevent unused argument(s) compilation warning if no assert_param check */
561 UNUSED(Bank);
562
563 /* NAND bank 3 registers configuration */
564 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
565 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT3_Pos) |
566 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD3_Pos) |
567 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ3_Pos)));
568
569 return HAL_OK;
570 }
571
572 /**
573 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
574 * parameters in the FMC_NAND_PCC_TimingTypeDef
575 * @param Device Pointer to NAND device instance
576 * @param Timing Pointer to NAND timing structure
577 * @param Bank NAND bank number
578 * @retval HAL status
579 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)580 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
581 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
582 {
583 /* Check the parameters */
584 assert_param(IS_FMC_NAND_DEVICE(Device));
585 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
586 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
587 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
588 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
589 assert_param(IS_FMC_NAND_BANK(Bank));
590
591 /* Prevent unused argument(s) compilation warning if no assert_param check */
592 UNUSED(Bank);
593
594 /* NAND bank 3 registers configuration */
595 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
596 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT3_Pos) |
597 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD3_Pos) |
598 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ3_Pos)));
599
600 return HAL_OK;
601 }
602
603 /**
604 * @brief DeInitializes the FMC_NAND device
605 * @param Device Pointer to NAND device instance
606 * @param Bank NAND bank number
607 * @retval HAL status
608 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)609 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
610 {
611 /* Check the parameters */
612 assert_param(IS_FMC_NAND_DEVICE(Device));
613 assert_param(IS_FMC_NAND_BANK(Bank));
614
615 /* Disable the NAND Bank */
616 __FMC_NAND_DISABLE(Device, Bank);
617
618 /* De-initialize the NAND Bank */
619 /* Prevent unused argument(s) compilation warning if no assert_param check */
620 UNUSED(Bank);
621
622 /* Set the FMC_NAND_BANK3 registers to their reset values */
623 WRITE_REG(Device->PCR, 0x00000018U);
624 WRITE_REG(Device->SR, 0x00000040U);
625 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
626 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
627
628 return HAL_OK;
629 }
630
631 /**
632 * @}
633 */
634
635 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
636 * @brief management functions
637 *
638 @verbatim
639 ==============================================================================
640 ##### FMC_NAND Control functions #####
641 ==============================================================================
642 [..]
643 This subsection provides a set of functions allowing to control dynamically
644 the FMC NAND interface.
645
646 @endverbatim
647 * @{
648 */
649
650
651 /**
652 * @brief Enables dynamically FMC_NAND ECC feature.
653 * @param Device Pointer to NAND device instance
654 * @param Bank NAND bank number
655 * @retval HAL status
656 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)657 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
658 {
659 /* Check the parameters */
660 assert_param(IS_FMC_NAND_DEVICE(Device));
661 assert_param(IS_FMC_NAND_BANK(Bank));
662
663 /* Enable ECC feature */
664 /* Prevent unused argument(s) compilation warning if no assert_param check */
665 UNUSED(Bank);
666
667 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
668
669 return HAL_OK;
670 }
671
672
673 /**
674 * @brief Disables dynamically FMC_NAND ECC feature.
675 * @param Device Pointer to NAND device instance
676 * @param Bank NAND bank number
677 * @retval HAL status
678 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)679 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
680 {
681 /* Check the parameters */
682 assert_param(IS_FMC_NAND_DEVICE(Device));
683 assert_param(IS_FMC_NAND_BANK(Bank));
684
685 /* Disable ECC feature */
686 /* Prevent unused argument(s) compilation warning if no assert_param check */
687 UNUSED(Bank);
688
689 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
690
691 return HAL_OK;
692 }
693
694 /**
695 * @brief Disables dynamically FMC_NAND ECC feature.
696 * @param Device Pointer to NAND device instance
697 * @param ECCval Pointer to ECC value
698 * @param Bank NAND bank number
699 * @param Timeout Timeout wait value
700 * @retval HAL status
701 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)702 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
703 uint32_t Timeout)
704 {
705 uint32_t tickstart;
706
707 /* Check the parameters */
708 assert_param(IS_FMC_NAND_DEVICE(Device));
709 assert_param(IS_FMC_NAND_BANK(Bank));
710
711 /* Get tick */
712 tickstart = HAL_GetTick();
713
714 /* Wait until FIFO is empty */
715 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
716 {
717 /* Check for the Timeout */
718 if (Timeout != HAL_MAX_DELAY)
719 {
720 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
721 {
722 return HAL_TIMEOUT;
723 }
724 }
725 }
726
727 /* Prevent unused argument(s) compilation warning if no assert_param check */
728 UNUSED(Bank);
729
730 /* Get the ECCR register value */
731 *ECCval = (uint32_t)Device->ECCR;
732
733 return HAL_OK;
734 }
735
736 /**
737 * @}
738 */
739
740
741
742 /** @defgroup FMC_LL_SDRAM
743 * @brief SDRAM Controller functions
744 *
745 @verbatim
746 ==============================================================================
747 ##### How to use SDRAM device driver #####
748 ==============================================================================
749 [..]
750 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
751 to run the SDRAM external devices.
752
753 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
754 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
755 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
756 (+) FMC SDRAM bank enable/disable write operation using the functions
757 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
758 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
759
760 @endverbatim
761 * @{
762 */
763
764 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
765 * @brief Initialization and Configuration functions
766 *
767 @verbatim
768 ==============================================================================
769 ##### Initialization and de_initialization functions #####
770 ==============================================================================
771 [..]
772 This section provides functions allowing to:
773 (+) Initialize and configure the FMC SDRAM interface
774 (+) De-initialize the FMC SDRAM interface
775 (+) Configure the FMC clock and associated GPIOs
776
777 @endverbatim
778 * @{
779 */
780
781 /**
782 * @brief Initializes the FMC_SDRAM device according to the specified
783 * control parameters in the FMC_SDRAM_InitTypeDef
784 * @param Device Pointer to SDRAM device instance
785 * @param Init Pointer to SDRAM Initialization structure
786 * @retval HAL status
787 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_InitTypeDef * Init)788 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
789 {
790 /* Check the parameters */
791 assert_param(IS_FMC_SDRAM_DEVICE(Device));
792 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
793 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
794 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
795 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
796 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
797 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
798 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
799 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
800 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
801 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
802
803 /* Set SDRAM bank configuration parameters */
804 if (Init->SDBank == FMC_SDRAM_BANK1)
805 {
806 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
807 SDCR_CLEAR_MASK,
808 (Init->ColumnBitsNumber |
809 Init->RowBitsNumber |
810 Init->MemoryDataWidth |
811 Init->InternalBankNumber |
812 Init->CASLatency |
813 Init->WriteProtection |
814 Init->SDClockPeriod |
815 Init->ReadBurst |
816 Init->ReadPipeDelay));
817 }
818 else /* FMC_Bank2_SDRAM */
819 {
820 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
821 FMC_SDCR1_SDCLK |
822 FMC_SDCR1_RBURST |
823 FMC_SDCR1_RPIPE,
824 (Init->SDClockPeriod |
825 Init->ReadBurst |
826 Init->ReadPipeDelay));
827
828 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
829 SDCR_CLEAR_MASK,
830 (Init->ColumnBitsNumber |
831 Init->RowBitsNumber |
832 Init->MemoryDataWidth |
833 Init->InternalBankNumber |
834 Init->CASLatency |
835 Init->WriteProtection));
836 }
837
838 return HAL_OK;
839 }
840
841
842 /**
843 * @brief Initializes the FMC_SDRAM device timing according to the specified
844 * parameters in the FMC_SDRAM_TimingTypeDef
845 * @param Device Pointer to SDRAM device instance
846 * @param Timing Pointer to SDRAM Timing structure
847 * @param Bank SDRAM bank number
848 * @retval HAL status
849 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)850 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
851 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
852 {
853 /* Check the parameters */
854 assert_param(IS_FMC_SDRAM_DEVICE(Device));
855 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
856 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
857 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
858 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
859 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
860 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
861 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
862 assert_param(IS_FMC_SDRAM_BANK(Bank));
863
864 /* Set SDRAM device timing parameters */
865 if (Bank == FMC_SDRAM_BANK1)
866 {
867 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
868 SDTR_CLEAR_MASK,
869 (((Timing->LoadToActiveDelay) - 1U) |
870 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
871 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
872 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
873 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
874 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
875 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
876 }
877 else /* FMC_Bank2_SDRAM */
878 {
879 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
880 FMC_SDTR1_TRC |
881 FMC_SDTR1_TRP,
882 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
883 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
884
885 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
886 SDTR_CLEAR_MASK,
887 (((Timing->LoadToActiveDelay) - 1U) |
888 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
889 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
890 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
891 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
892 }
893
894 return HAL_OK;
895 }
896
897 /**
898 * @brief DeInitializes the FMC_SDRAM peripheral
899 * @param Device Pointer to SDRAM device instance
900 * @retval HAL status
901 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)902 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
903 {
904 /* Check the parameters */
905 assert_param(IS_FMC_SDRAM_DEVICE(Device));
906 assert_param(IS_FMC_SDRAM_BANK(Bank));
907
908 /* De-initialize the SDRAM device */
909 Device->SDCR[Bank] = 0x000002D0U;
910 Device->SDTR[Bank] = 0x0FFFFFFFU;
911 Device->SDCMR = 0x00000000U;
912 Device->SDRTR = 0x00000000U;
913 Device->SDSR = 0x00000000U;
914
915 return HAL_OK;
916 }
917
918 /**
919 * @}
920 */
921
922 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
923 * @brief management functions
924 *
925 @verbatim
926 ==============================================================================
927 ##### FMC_SDRAM Control functions #####
928 ==============================================================================
929 [..]
930 This subsection provides a set of functions allowing to control dynamically
931 the FMC SDRAM interface.
932
933 @endverbatim
934 * @{
935 */
936
937 /**
938 * @brief Enables dynamically FMC_SDRAM write protection.
939 * @param Device Pointer to SDRAM device instance
940 * @param Bank SDRAM bank number
941 * @retval HAL status
942 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)943 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
944 {
945 /* Check the parameters */
946 assert_param(IS_FMC_SDRAM_DEVICE(Device));
947 assert_param(IS_FMC_SDRAM_BANK(Bank));
948
949 /* Enable write protection */
950 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
951
952 return HAL_OK;
953 }
954
955 /**
956 * @brief Disables dynamically FMC_SDRAM write protection.
957 * @param hsdram FMC_SDRAM handle
958 * @retval HAL status
959 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)960 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
961 {
962 /* Check the parameters */
963 assert_param(IS_FMC_SDRAM_DEVICE(Device));
964 assert_param(IS_FMC_SDRAM_BANK(Bank));
965
966 /* Disable write protection */
967 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
968
969 return HAL_OK;
970 }
971
972 /**
973 * @brief Send Command to the FMC SDRAM bank
974 * @param Device Pointer to SDRAM device instance
975 * @param Command Pointer to SDRAM command structure
976 * @param Timing Pointer to SDRAM Timing structure
977 * @param Timeout Timeout wait value
978 * @retval HAL state
979 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)980 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
981 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
982 {
983 /* Check the parameters */
984 assert_param(IS_FMC_SDRAM_DEVICE(Device));
985 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
986 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
987 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
988 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
989
990 /* Set command register */
991 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
992 ((Command->CommandMode) | (Command->CommandTarget) |
993 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
994 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
995 /* Prevent unused argument(s) compilation warning */
996 UNUSED(Timeout);
997 return HAL_OK;
998 }
999
1000 /**
1001 * @brief Program the SDRAM Memory Refresh rate.
1002 * @param Device Pointer to SDRAM device instance
1003 * @param RefreshRate The SDRAM refresh rate value.
1004 * @retval HAL state
1005 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1006 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1007 {
1008 /* Check the parameters */
1009 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1010 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1011
1012 /* Set the refresh rate in command register */
1013 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1014
1015 return HAL_OK;
1016 }
1017
1018 /**
1019 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1020 * @param Device Pointer to SDRAM device instance
1021 * @param AutoRefreshNumber Specifies the auto Refresh number.
1022 * @retval None
1023 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1024 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1025 uint32_t AutoRefreshNumber)
1026 {
1027 /* Check the parameters */
1028 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1029 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1030
1031 /* Set the Auto-refresh number in command register */
1032 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1033
1034 return HAL_OK;
1035 }
1036
1037 /**
1038 * @brief Returns the indicated FMC SDRAM bank mode status.
1039 * @param Device Pointer to SDRAM device instance
1040 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1041 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1042 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1043 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1044 * FMC_SDRAM_POWER_DOWN_MODE.
1045 */
FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1046 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1047 {
1048 uint32_t tmpreg;
1049
1050 /* Check the parameters */
1051 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1052 assert_param(IS_FMC_SDRAM_BANK(Bank));
1053
1054 /* Get the corresponding bank mode */
1055 if (Bank == FMC_SDRAM_BANK1)
1056 {
1057 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1058 }
1059 else
1060 {
1061 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1062 }
1063
1064 /* Return the mode status */
1065 return tmpreg;
1066 }
1067
1068 /**
1069 * @}
1070 */
1071
1072 /**
1073 * @}
1074 */
1075
1076
1077 /**
1078 * @}
1079 */
1080
1081 /**
1082 * @}
1083 */
1084
1085 #endif /* HAL_NOR_MODULE_ENABLED */
1086 /**
1087 * @}
1088 */
1089 /**
1090 * @}
1091 */
1092
