1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fsmc.c
4 * @author MCD Application Team
5 * @brief FSMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2016 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FSMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FSMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND/PC Card memory controller
31
32 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
33 memories and 16-bit PC memory cards. Its main purposes are:
34 (+) to translate AHB transactions into the appropriate external device protocol
35 (+) to meet the access time requirements of the external memory devices
36
37 [..] All external memories share the addresses, data and control signals with the controller.
38 Each external device is accessed by means of a unique Chip Select. The FSMC performs
39 only one access at a time to an external device.
40 The main features of the FSMC controller are the following:
41 (+) Interface with static-memory mapped devices including:
42 (++) Static random access memory (SRAM)
43 (++) Read-only memory (ROM)
44 (++) NOR Flash memory/OneNAND Flash memory
45 (++) PSRAM (4 memory banks)
46 (++) 16-bit PC Card compatible devices
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Independent Chip Select control for each memory bank
50 (+) Independent configuration for each memory bank
51
52 @endverbatim
53 ******************************************************************************
54 */
55
56 /* Includes ------------------------------------------------------------------*/
57 #include "stm32f4xx_hal.h"
58
59 /** @addtogroup STM32F4xx_HAL_Driver
60 * @{
61 */
62 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
63
64 /** @defgroup FSMC_LL FSMC Low Layer
65 * @brief FSMC driver modules
66 * @{
67 */
68
69 /* Private typedef -----------------------------------------------------------*/
70 /* Private define ------------------------------------------------------------*/
71
72 /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
73 * @{
74 */
75
76 /* ----------------------- FSMC registers bit mask --------------------------- */
77
78 #if defined(FSMC_Bank1)
79 /* --- BCR Register ---*/
80 /* BCR register clear mask */
81
82 /* --- BTR Register ---*/
83 /* BTR register clear mask */
84 #define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD |\
85 FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\
86 FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT |\
87 FSMC_BTR1_ACCMOD))
88
89 /* --- BWTR Register ---*/
90 /* BWTR register clear mask */
91 #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD |\
92 FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\
93 FSMC_BWTR1_ACCMOD))
94 #endif /* FSMC_Bank1 */
95 #if defined(FSMC_Bank2_3)
96
97 #if defined (FSMC_PCR_PWAITEN)
98 /* --- PCR Register ---*/
99 /* PCR register clear mask */
100 #define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR_PWAITEN | FSMC_PCR_PBKEN | \
101 FSMC_PCR_PTYP | FSMC_PCR_PWID | \
102 FSMC_PCR_ECCEN | FSMC_PCR_TCLR | \
103 FSMC_PCR_TAR | FSMC_PCR_ECCPS))
104 /* --- PMEM Register ---*/
105 /* PMEM register clear mask */
106 #define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM_MEMSET2 | FSMC_PMEM_MEMWAIT2 |\
107 FSMC_PMEM_MEMHOLD2 | FSMC_PMEM_MEMHIZ2))
108
109 /* --- PATT Register ---*/
110 /* PATT register clear mask */
111 #define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT_ATTSET2 | FSMC_PATT_ATTWAIT2 |\
112 FSMC_PATT_ATTHOLD2 | FSMC_PATT_ATTHIZ2))
113 #else
114 /* --- PCR Register ---*/
115 /* PCR register clear mask */
116 #define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | \
117 FSMC_PCR2_PTYP | FSMC_PCR2_PWID | \
118 FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
119 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS))
120 /* --- PMEM Register ---*/
121 /* PMEM register clear mask */
122 #define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 |\
123 FSMC_PMEM2_MEMHOLD2 | FSMC_PMEM2_MEMHIZ2))
124
125 /* --- PATT Register ---*/
126 /* PATT register clear mask */
127 #define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 |\
128 FSMC_PATT2_ATTHOLD2 | FSMC_PATT2_ATTHIZ2))
129
130 #endif /* FSMC_PCR_PWAITEN */
131 #endif /* FSMC_Bank2_3 */
132 #if defined(FSMC_Bank4)
133 /* --- PCR Register ---*/
134 /* PCR register clear mask */
135 #define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \
136 FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \
137 FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \
138 FSMC_PCR4_TAR | FSMC_PCR4_ECCPS))
139 /* --- PMEM Register ---*/
140 /* PMEM register clear mask */
141 #define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\
142 FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
143
144 /* --- PATT Register ---*/
145 /* PATT register clear mask */
146 #define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\
147 FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
148
149 /* --- PIO4 Register ---*/
150 /* PIO4 register clear mask */
151 #define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
152 FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
153
154 #endif /* FSMC_Bank4 */
155
156 /**
157 * @}
158 */
159
160 /* Private macro -------------------------------------------------------------*/
161 /* Private variables ---------------------------------------------------------*/
162 /* Private function prototypes -----------------------------------------------*/
163 /* Exported functions --------------------------------------------------------*/
164
165 /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
166 * @{
167 */
168
169 #if defined(FSMC_Bank1)
170
171 /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
172 * @brief NORSRAM Controller functions
173 *
174 @verbatim
175 ==============================================================================
176 ##### How to use NORSRAM device driver #####
177 ==============================================================================
178
179 [..]
180 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
181 to run the NORSRAM external devices.
182
183 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
184 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
185 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
186 (+) FSMC NORSRAM bank extended timing configuration using the function
187 FSMC_NORSRAM_Extended_Timing_Init()
188 (+) FSMC NORSRAM bank enable/disable write operation using the functions
189 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
190
191 @endverbatim
192 * @{
193 */
194
195 /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
196 * @brief Initialization and Configuration functions
197 *
198 @verbatim
199 ==============================================================================
200 ##### Initialization and de_initialization functions #####
201 ==============================================================================
202 [..]
203 This section provides functions allowing to:
204 (+) Initialize and configure the FSMC NORSRAM interface
205 (+) De-initialize the FSMC NORSRAM interface
206 (+) Configure the FSMC clock and associated GPIOs
207
208 @endverbatim
209 * @{
210 */
211
212 /**
213 * @brief Initialize the FSMC_NORSRAM device according to the specified
214 * control parameters in the FSMC_NORSRAM_InitTypeDef
215 * @param Device Pointer to NORSRAM device instance
216 * @param Init Pointer to NORSRAM Initialization structure
217 * @retval HAL status
218 */
FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_InitTypeDef * Init)219 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
220 FSMC_NORSRAM_InitTypeDef *Init)
221 {
222 uint32_t flashaccess;
223 uint32_t btcr_reg;
224 uint32_t mask;
225
226 /* Check the parameters */
227 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
228 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
229 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
230 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
231 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
232 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
233 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
234 #if defined(FSMC_BCR1_WRAPMOD)
235 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
236 #endif /* FSMC_BCR1_WRAPMOD */
237 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
238 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
239 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
240 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
241 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
242 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
243 #if defined(FSMC_BCR1_CCLKEN)
244 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
245 #endif
246 #if defined(FSMC_BCR1_WFDIS)
247 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
248 #endif /* FSMC_BCR1_WFDIS */
249 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
250
251 /* Disable NORSRAM Device */
252 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
253
254 /* Set NORSRAM device control parameters */
255 if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
256 {
257 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
258 }
259 else
260 {
261 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
262 }
263
264 btcr_reg = (flashaccess | \
265 Init->DataAddressMux | \
266 Init->MemoryType | \
267 Init->MemoryDataWidth | \
268 Init->BurstAccessMode | \
269 Init->WaitSignalPolarity | \
270 Init->WaitSignalActive | \
271 Init->WriteOperation | \
272 Init->WaitSignal | \
273 Init->ExtendedMode | \
274 Init->AsynchronousWait | \
275 Init->WriteBurst);
276
277 #if defined(FSMC_BCR1_WRAPMOD)
278 btcr_reg |= Init->WrapMode;
279 #endif /* FSMC_BCR1_WRAPMOD */
280 #if defined(FSMC_BCR1_CCLKEN)
281 btcr_reg |= Init->ContinuousClock;
282 #endif /* FSMC_BCR1_CCLKEN */
283 #if defined(FSMC_BCR1_WFDIS)
284 btcr_reg |= Init->WriteFifo;
285 #endif /* FSMC_BCR1_WFDIS */
286 btcr_reg |= Init->PageSize;
287
288 mask = (FSMC_BCR1_MBKEN |
289 FSMC_BCR1_MUXEN |
290 FSMC_BCR1_MTYP |
291 FSMC_BCR1_MWID |
292 FSMC_BCR1_FACCEN |
293 FSMC_BCR1_BURSTEN |
294 FSMC_BCR1_WAITPOL |
295 FSMC_BCR1_WAITCFG |
296 FSMC_BCR1_WREN |
297 FSMC_BCR1_WAITEN |
298 FSMC_BCR1_EXTMOD |
299 FSMC_BCR1_ASYNCWAIT |
300 FSMC_BCR1_CBURSTRW);
301
302 #if defined(FSMC_BCR1_WRAPMOD)
303 mask |= FSMC_BCR1_WRAPMOD;
304 #endif /* FSMC_BCR1_WRAPMOD */
305 #if defined(FSMC_BCR1_CCLKEN)
306 mask |= FSMC_BCR1_CCLKEN;
307 #endif
308 #if defined(FSMC_BCR1_WFDIS)
309 mask |= FSMC_BCR1_WFDIS;
310 #endif /* FSMC_BCR1_WFDIS */
311 mask |= FSMC_BCR1_CPSIZE;
312
313 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
314
315 #if defined(FSMC_BCR1_CCLKEN)
316 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
317 if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
318 {
319 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock);
320 }
321 #endif
322 #if defined(FSMC_BCR1_WFDIS)
323
324 if (Init->NSBank != FSMC_NORSRAM_BANK1)
325 {
326 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
327 SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
328 }
329 #endif /* FSMC_BCR1_WFDIS */
330
331 return HAL_OK;
332 }
333
334 /**
335 * @brief DeInitialize the FSMC_NORSRAM peripheral
336 * @param Device Pointer to NORSRAM device instance
337 * @param ExDevice Pointer to NORSRAM extended mode device instance
338 * @param Bank NORSRAM bank number
339 * @retval HAL status
340 */
FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)341 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
342 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
343 {
344 /* Check the parameters */
345 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
346 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
347 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
348
349 /* Disable the FSMC_NORSRAM device */
350 __FSMC_NORSRAM_DISABLE(Device, Bank);
351
352 /* De-initialize the FSMC_NORSRAM device */
353 /* FSMC_NORSRAM_BANK1 */
354 if (Bank == FSMC_NORSRAM_BANK1)
355 {
356 Device->BTCR[Bank] = 0x000030DBU;
357 }
358 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
359 else
360 {
361 Device->BTCR[Bank] = 0x000030D2U;
362 }
363
364 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
365 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
366
367 return HAL_OK;
368 }
369
370 /**
371 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
372 * parameters in the FSMC_NORSRAM_TimingTypeDef
373 * @param Device Pointer to NORSRAM device instance
374 * @param Timing Pointer to NORSRAM Timing structure
375 * @param Bank NORSRAM bank number
376 * @retval HAL status
377 */
FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)378 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
379 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
380 {
381 #if defined(FSMC_BCR1_CCLKEN)
382 uint32_t tmpr;
383 #endif
384
385 /* Check the parameters */
386 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
387 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
388 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
389 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
390 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
391 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
392 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
393 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
394 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
395
396 /* Set FSMC_NORSRAM device timing parameters */
397 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
398 ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) |
399 ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) |
400 ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) |
401 (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) |
402 (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) |
403 (Timing->AccessMode)));
404
405 #if defined(FSMC_BCR1_CCLKEN)
406 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
407 if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
408 {
409 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos));
410 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos);
411 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr);
412 }
413
414 #endif
415 return HAL_OK;
416 }
417
418 /**
419 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
420 * parameters in the FSMC_NORSRAM_TimingTypeDef
421 * @param Device Pointer to NORSRAM device instance
422 * @param Timing Pointer to NORSRAM Timing structure
423 * @param Bank NORSRAM bank number
424 * @param ExtendedMode FSMC Extended Mode
425 * This parameter can be one of the following values:
426 * @arg FSMC_EXTENDED_MODE_DISABLE
427 * @arg FSMC_EXTENDED_MODE_ENABLE
428 * @retval HAL status
429 */
FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)430 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
431 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
432 uint32_t ExtendedMode)
433 {
434 /* Check the parameters */
435 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
436
437 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
438 if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
439 {
440 /* Check the parameters */
441 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
442 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
443 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
444 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
445 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
446 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
447 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
448
449 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
450 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
451 ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) |
452 ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) |
453 Timing->AccessMode |
454 ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos)));
455 }
456 else
457 {
458 Device->BWTR[Bank] = 0x0FFFFFFFU;
459 }
460
461 return HAL_OK;
462 }
463 /**
464 * @}
465 */
466
467 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
468 * @brief management functions
469 *
470 @verbatim
471 ==============================================================================
472 ##### FSMC_NORSRAM Control functions #####
473 ==============================================================================
474 [..]
475 This subsection provides a set of functions allowing to control dynamically
476 the FSMC NORSRAM interface.
477
478 @endverbatim
479 * @{
480 */
481
482 /**
483 * @brief Enables dynamically FSMC_NORSRAM write operation.
484 * @param Device Pointer to NORSRAM device instance
485 * @param Bank NORSRAM bank number
486 * @retval HAL status
487 */
FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)488 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
489 {
490 /* Check the parameters */
491 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
492 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
493
494 /* Enable write operation */
495 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
496
497 return HAL_OK;
498 }
499
500 /**
501 * @brief Disables dynamically FSMC_NORSRAM write operation.
502 * @param Device Pointer to NORSRAM device instance
503 * @param Bank NORSRAM bank number
504 * @retval HAL status
505 */
FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)506 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
507 {
508 /* Check the parameters */
509 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
510 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
511
512 /* Disable write operation */
513 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
514
515 return HAL_OK;
516 }
517
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525 #endif /* FSMC_Bank1 */
526
527 #if defined(FSMC_Bank2_3)
528
529 /** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
530 * @brief NAND Controller functions
531 *
532 @verbatim
533 ==============================================================================
534 ##### How to use NAND device driver #####
535 ==============================================================================
536 [..]
537 This driver contains a set of APIs to interface with the FSMC NAND banks in order
538 to run the NAND external devices.
539
540 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
541 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
542 (+) FSMC NAND bank common space timing configuration using the function
543 FSMC_NAND_CommonSpace_Timing_Init()
544 (+) FSMC NAND bank attribute space timing configuration using the function
545 FSMC_NAND_AttributeSpace_Timing_Init()
546 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
547 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
548 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
549
550 @endverbatim
551 * @{
552 */
553
554 /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
555 * @brief Initialization and Configuration functions
556 *
557 @verbatim
558 ==============================================================================
559 ##### Initialization and de_initialization functions #####
560 ==============================================================================
561 [..]
562 This section provides functions allowing to:
563 (+) Initialize and configure the FSMC NAND interface
564 (+) De-initialize the FSMC NAND interface
565 (+) Configure the FSMC clock and associated GPIOs
566
567 @endverbatim
568 * @{
569 */
570
571 /**
572 * @brief Initializes the FSMC_NAND device according to the specified
573 * control parameters in the FSMC_NAND_HandleTypeDef
574 * @param Device Pointer to NAND device instance
575 * @param Init Pointer to NAND Initialization structure
576 * @retval HAL status
577 */
FSMC_NAND_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_InitTypeDef * Init)578 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
579 {
580 /* Check the parameters */
581 assert_param(IS_FSMC_NAND_DEVICE(Device));
582 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
583 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
584 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
585 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
586 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
587 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
588 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
589
590 /* Set NAND device control parameters */
591 if (Init->NandBank == FSMC_NAND_BANK2)
592 {
593 /* NAND bank 2 registers configuration */
594 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
595 FSMC_PCR_MEMORY_TYPE_NAND |
596 Init->MemoryDataWidth |
597 Init->EccComputation |
598 Init->ECCPageSize |
599 ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
600 ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos)));
601 }
602 else
603 {
604 /* NAND bank 3 registers configuration */
605 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
606 FSMC_PCR_MEMORY_TYPE_NAND |
607 Init->MemoryDataWidth |
608 Init->EccComputation |
609 Init->ECCPageSize |
610 ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
611 ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos)));
612 }
613
614 return HAL_OK;
615 }
616
617 /**
618 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
619 * parameters in the FSMC_NAND_PCC_TimingTypeDef
620 * @param Device Pointer to NAND device instance
621 * @param Timing Pointer to NAND timing structure
622 * @param Bank NAND bank number
623 * @retval HAL status
624 */
FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)625 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
626 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
627 {
628 /* Check the parameters */
629 assert_param(IS_FSMC_NAND_DEVICE(Device));
630 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
631 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
632 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
633 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
634 assert_param(IS_FSMC_NAND_BANK(Bank));
635
636 /* Set FSMC_NAND device timing parameters */
637 if (Bank == FSMC_NAND_BANK2)
638 {
639 /* NAND bank 2 registers configuration */
640 MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |
641 ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
642 ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
643 ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos)));
644 }
645 else
646 {
647 /* NAND bank 3 registers configuration */
648 MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |
649 ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
650 ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
651 ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos)));
652 }
653
654 return HAL_OK;
655 }
656
657 /**
658 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
659 * parameters in the FSMC_NAND_PCC_TimingTypeDef
660 * @param Device Pointer to NAND device instance
661 * @param Timing Pointer to NAND timing structure
662 * @param Bank NAND bank number
663 * @retval HAL status
664 */
FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)665 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
666 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
667 {
668 /* Check the parameters */
669 assert_param(IS_FSMC_NAND_DEVICE(Device));
670 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
671 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
672 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
673 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
674 assert_param(IS_FSMC_NAND_BANK(Bank));
675
676 /* Set FSMC_NAND device timing parameters */
677 if (Bank == FSMC_NAND_BANK2)
678 {
679 /* NAND bank 2 registers configuration */
680 MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |
681 ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
682 ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
683 ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos)));
684 }
685 else
686 {
687 /* NAND bank 3 registers configuration */
688 MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |
689 ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
690 ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
691 ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos)));
692 }
693
694 return HAL_OK;
695 }
696
697 /**
698 * @brief DeInitializes the FSMC_NAND device
699 * @param Device Pointer to NAND device instance
700 * @param Bank NAND bank number
701 * @retval HAL status
702 */
FSMC_NAND_DeInit(FSMC_NAND_TypeDef * Device,uint32_t Bank)703 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
704 {
705 /* Check the parameters */
706 assert_param(IS_FSMC_NAND_DEVICE(Device));
707 assert_param(IS_FSMC_NAND_BANK(Bank));
708
709 /* Disable the NAND Bank */
710 __FSMC_NAND_DISABLE(Device, Bank);
711
712 /* De-initialize the NAND Bank */
713 if (Bank == FSMC_NAND_BANK2)
714 {
715 /* Set the FSMC_NAND_BANK2 registers to their reset values */
716 WRITE_REG(Device->PCR2, 0x00000018U);
717 WRITE_REG(Device->SR2, 0x00000040U);
718 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
719 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
720 }
721 /* FSMC_Bank3_NAND */
722 else
723 {
724 /* Set the FSMC_NAND_BANK3 registers to their reset values */
725 WRITE_REG(Device->PCR3, 0x00000018U);
726 WRITE_REG(Device->SR3, 0x00000040U);
727 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
728 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
729 }
730
731 return HAL_OK;
732 }
733
734 /**
735 * @}
736 */
737
738 /** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
739 * @brief management functions
740 *
741 @verbatim
742 ==============================================================================
743 ##### FSMC_NAND Control functions #####
744 ==============================================================================
745 [..]
746 This subsection provides a set of functions allowing to control dynamically
747 the FSMC NAND interface.
748
749 @endverbatim
750 * @{
751 */
752
753
754 /**
755 * @brief Enables dynamically FSMC_NAND ECC feature.
756 * @param Device Pointer to NAND device instance
757 * @param Bank NAND bank number
758 * @retval HAL status
759 */
FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef * Device,uint32_t Bank)760 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
761 {
762 /* Check the parameters */
763 assert_param(IS_FSMC_NAND_DEVICE(Device));
764 assert_param(IS_FSMC_NAND_BANK(Bank));
765
766 /* Enable ECC feature */
767 if (Bank == FSMC_NAND_BANK2)
768 {
769 SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
770 }
771 else
772 {
773 SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
774 }
775
776 return HAL_OK;
777 }
778
779
780 /**
781 * @brief Disables dynamically FSMC_NAND ECC feature.
782 * @param Device Pointer to NAND device instance
783 * @param Bank NAND bank number
784 * @retval HAL status
785 */
FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef * Device,uint32_t Bank)786 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
787 {
788 /* Check the parameters */
789 assert_param(IS_FSMC_NAND_DEVICE(Device));
790 assert_param(IS_FSMC_NAND_BANK(Bank));
791
792 /* Disable ECC feature */
793 if (Bank == FSMC_NAND_BANK2)
794 {
795 CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
796 }
797 else
798 {
799 CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
800 }
801
802 return HAL_OK;
803 }
804
805 /**
806 * @brief Disables dynamically FSMC_NAND ECC feature.
807 * @param Device Pointer to NAND device instance
808 * @param ECCval Pointer to ECC value
809 * @param Bank NAND bank number
810 * @param Timeout Timeout wait value
811 * @retval HAL status
812 */
FSMC_NAND_GetECC(FSMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)813 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
814 uint32_t Timeout)
815 {
816 uint32_t tickstart;
817
818 /* Check the parameters */
819 assert_param(IS_FSMC_NAND_DEVICE(Device));
820 assert_param(IS_FSMC_NAND_BANK(Bank));
821
822 /* Get tick */
823 tickstart = HAL_GetTick();
824
825 /* Wait until FIFO is empty */
826 while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
827 {
828 /* Check for the Timeout */
829 if (Timeout != HAL_MAX_DELAY)
830 {
831 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
832 {
833 return HAL_TIMEOUT;
834 }
835 }
836 }
837
838 if (Bank == FSMC_NAND_BANK2)
839 {
840 /* Get the ECCR2 register value */
841 *ECCval = (uint32_t)Device->ECCR2;
842 }
843 else
844 {
845 /* Get the ECCR3 register value */
846 *ECCval = (uint32_t)Device->ECCR3;
847 }
848
849 return HAL_OK;
850 }
851
852 /**
853 * @}
854 */
855 #endif /* FSMC_Bank2_3 */
856
857 #if defined(FSMC_Bank4)
858
859 /** @addtogroup FSMC_LL_PCCARD
860 * @brief PCCARD Controller functions
861 *
862 @verbatim
863 ==============================================================================
864 ##### How to use PCCARD device driver #####
865 ==============================================================================
866 [..]
867 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
868 to run the PCCARD/compact flash external devices.
869
870 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
871 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
872 (+) FSMC PCCARD bank common space timing configuration using the function
873 FSMC_PCCARD_CommonSpace_Timing_Init()
874 (+) FSMC PCCARD bank attribute space timing configuration using the function
875 FSMC_PCCARD_AttributeSpace_Timing_Init()
876 (+) FSMC PCCARD bank IO space timing configuration using the function
877 FSMC_PCCARD_IOSpace_Timing_Init()
878 @endverbatim
879 * @{
880 */
881
882 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
883 * @brief Initialization and Configuration functions
884 *
885 @verbatim
886 ==============================================================================
887 ##### Initialization and de_initialization functions #####
888 ==============================================================================
889 [..]
890 This section provides functions allowing to:
891 (+) Initialize and configure the FSMC PCCARD interface
892 (+) De-initialize the FSMC PCCARD interface
893 (+) Configure the FSMC clock and associated GPIOs
894
895 @endverbatim
896 * @{
897 */
898
899 /**
900 * @brief Initializes the FSMC_PCCARD device according to the specified
901 * control parameters in the FSMC_PCCARD_HandleTypeDef
902 * @param Device Pointer to PCCARD device instance
903 * @param Init Pointer to PCCARD Initialization structure
904 * @retval HAL status
905 */
FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef * Device,FSMC_PCCARD_InitTypeDef * Init)906 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
907 {
908 /* Check the parameters */
909 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
910 #if defined(FSMC_Bank2_3)
911 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
912 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
913 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
914 #endif /* FSMC_Bank2_3 */
915
916 /* Set FSMC_PCCARD device control parameters */
917 MODIFY_REG(Device->PCR4,
918 (FSMC_PCR4_PTYP |
919 FSMC_PCR4_PWAITEN |
920 FSMC_PCR4_PWID |
921 FSMC_PCR4_TCLR |
922 FSMC_PCR4_TAR),
923 (FSMC_PCR_MEMORY_TYPE_PCCARD |
924 Init->Waitfeature |
925 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
926 (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) |
927 (Init->TARSetupTime << FSMC_PCR4_TAR_Pos)));
928
929 return HAL_OK;
930 }
931
932 /**
933 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
934 * parameters in the FSMC_NAND_PCC_TimingTypeDef
935 * @param Device Pointer to PCCARD device instance
936 * @param Timing Pointer to PCCARD timing structure
937 * @retval HAL status
938 */
FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)939 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
940 FSMC_NAND_PCC_TimingTypeDef *Timing)
941 {
942 /* Check the parameters */
943 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
944 #if defined(FSMC_Bank2_3)
945 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
946 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
947 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
948 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
949 #endif /* FSMC_Bank2_3 */
950
951 /* Set PCCARD timing parameters */
952 MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
953 (Timing->SetupTime |
954 ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) |
955 ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) |
956 ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos)));
957
958 return HAL_OK;
959 }
960
961 /**
962 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
963 * parameters in the FSMC_NAND_PCC_TimingTypeDef
964 * @param Device Pointer to PCCARD device instance
965 * @param Timing Pointer to PCCARD timing structure
966 * @retval HAL status
967 */
FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)968 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
969 FSMC_NAND_PCC_TimingTypeDef *Timing)
970 {
971 /* Check the parameters */
972 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
973 #if defined(FSMC_Bank2_3)
974 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
975 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
976 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
977 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
978 #endif /* FSMC_Bank2_3 */
979
980 /* Set PCCARD timing parameters */
981 MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
982 (Timing->SetupTime |
983 ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) |
984 ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) |
985 ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos)));
986
987 return HAL_OK;
988 }
989
990 /**
991 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
992 * parameters in the FSMC_NAND_PCC_TimingTypeDef
993 * @param Device Pointer to PCCARD device instance
994 * @param Timing Pointer to PCCARD timing structure
995 * @retval HAL status
996 */
FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)997 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
998 FSMC_NAND_PCC_TimingTypeDef *Timing)
999 {
1000 /* Check the parameters */
1001 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
1002 #if defined(FSMC_Bank2_3)
1003 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
1004 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
1005 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
1006 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
1007 #endif /* FSMC_Bank2_3 */
1008
1009 /* Set FSMC_PCCARD device timing parameters */
1010 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
1011 (Timing->SetupTime |
1012 (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) |
1013 (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) |
1014 (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
1015
1016 return HAL_OK;
1017 }
1018
1019 /**
1020 * @brief DeInitializes the FSMC_PCCARD device
1021 * @param Device Pointer to PCCARD device instance
1022 * @retval HAL status
1023 */
FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef * Device)1024 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
1025 {
1026 /* Check the parameters */
1027 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
1028
1029 /* Disable the FSMC_PCCARD device */
1030 __FSMC_PCCARD_DISABLE(Device);
1031
1032 /* De-initialize the FSMC_PCCARD device */
1033 Device->PCR4 = 0x00000018U;
1034 Device->SR4 = 0x00000040U;
1035 Device->PMEM4 = 0xFCFCFCFCU;
1036 Device->PATT4 = 0xFCFCFCFCU;
1037 Device->PIO4 = 0xFCFCFCFCU;
1038
1039 return HAL_OK;
1040 }
1041
1042 /**
1043 * @}
1044 */
1045 #endif /* FSMC_Bank4 */
1046
1047
1048 /**
1049 * @}
1050 */
1051
1052 /**
1053 * @}
1054 */
1055
1056 #endif /* HAL_NOR_MODULE_ENABLED */
1057 /**
1058 * @}
1059 */
1060 /**
1061 * @}
1062 */
1063
