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Searched refs:Device (Results 1 – 25 of 29) sorted by relevance

12

/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c238 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
246 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
271 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
332 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
338 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
346 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
360 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
364 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
369 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
375 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
[all …]
Dstm32f4xx_ll_fsmc.c219 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_Init() argument
227 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
252 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); in FSMC_NORSRAM_Init()
313 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
319 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock); in FSMC_NORSRAM_Init()
327 SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FSMC_NORSRAM_Init()
341 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_DeInit() argument
345 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_DeInit()
350 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
356 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c190 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
198 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
218 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
272 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
278 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
288 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
294 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
298 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
302 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c189 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
197 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
215 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
273 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
286 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
290 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
295 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
301 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c189 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
197 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
215 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
273 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
286 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
290 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
295 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
301 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c200 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
208 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
225 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
270 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
275 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
288 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
292 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
297 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
303 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
308 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c207 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_Init() argument
215 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
232 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); in FSMC_NORSRAM_Init()
277 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
290 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_DeInit() argument
294 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_DeInit()
299 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
305 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
310 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
313 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c195 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_Init() argument
203 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
219 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); in FSMC_NORSRAM_Init()
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
275 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_DeInit() argument
279 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_DeInit()
284 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
290 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
295 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
298 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c173 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
181 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
201 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
250 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
255 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
261 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
271 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
277 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
281 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
285 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c177 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
185 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
205 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
254 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
259 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
265 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
275 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
281 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
285 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
289 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c172 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
180 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
200 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
249 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
254 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
260 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
270 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
276 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
280 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
284 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c190 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
198 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
224 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
281 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
286 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
293 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
305 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
311 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
315 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
319 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c158 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) in FMC_NORSRAM_Init() argument
163 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
182 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
194 MODIFY_REG(Device->BTCR[Init->NSBank], in FMC_NORSRAM_Init()
230 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
240 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
246 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
250 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
254 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
258 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); in FMC_NORSRAM_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c155 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_Init() argument
163 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_Init()
180 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); in FSMC_NORSRAM_Init()
225 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
238 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, in FSMC_NORSRAM_DeInit() argument
242 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); in FSMC_NORSRAM_DeInit()
247 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
253 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
258 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
261 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_fmc.h1285 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1287 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1289 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1292 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1301 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1302 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1318 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1319 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1321 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1323 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
Dstm32f4xx_ll_fsmc.h988 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
990 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
992 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
995 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
1004 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1005 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1021 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
1022 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
1024 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
1026 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_fmc.h1058 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1060 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1062 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1065 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1074 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1075 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1089 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1090 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1092 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1094 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_fmc.h1047 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1049 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1051 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1054 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1063 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1064 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1078 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1079 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1081 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1083 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_fmc.h1090 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1092 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1094 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1097 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1106 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1107 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1121 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1122 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1124 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1126 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_fsmc.h797 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
799 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
801 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
804 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
813 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
814 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
828 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
829 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
831 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
833 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_fmc.h848 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
850 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
852 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
855 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
864 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
865 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
881 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
882 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
884 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
886 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_fsmc.h865 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
867 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
869 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
872 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
881 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
882 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
898 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
899 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
901 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
903 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_fmc.h789 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
791 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
793 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
796 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
805 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
806 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
822 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
823 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
825 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
827 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_fmc.h779 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
781 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
783 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
786 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
795 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
796 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
812 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
813 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
815 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
817 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_fmc.h759 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
761 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
763 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
766 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
775 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
776 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
790 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
791 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
793 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
795 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]

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