1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_ll_fsmc.h 4 * @author MCD Application Team 5 * @brief Header file of FSMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_LL_FSMC_H 21 #define STM32F4xx_LL_FSMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FSMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FSMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FSMC_Bank1) 42 43 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FSMC_NORSRAM_BANK4)) 47 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) 52 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FSMC_PAGE_SIZE_1024)) 60 #if defined(FSMC_BCR1_WFDIS) 61 #define IS_FSMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FSMC_WRITE_FIFO_DISABLE) || \ 62 ((__FIFO__) == FSMC_WRITE_FIFO_ENABLE)) 63 #endif /* FSMC_BCR1_WFDIS */ 64 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ 65 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ 66 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ 67 ((__MODE__) == FSMC_ACCESS_MODE_D)) 68 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ 69 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) 70 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ 71 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) 72 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ 73 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 74 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ 75 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 76 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ 77 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) 78 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ 79 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 80 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ 81 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) 82 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 83 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) 84 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 85 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ 86 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 87 #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 88 ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 89 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 91 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 92 #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 93 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 95 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) 96 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) 97 98 #endif /* FSMC_Bank1 */ 99 #if defined(FSMC_Bank2_3) 100 101 #define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \ 102 ((__BANK__) == FSMC_NAND_BANK3)) 103 #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ 104 ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) 105 #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ 106 ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) 107 #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ 108 ((__STATE__) == FSMC_NAND_ECC_ENABLE)) 109 110 #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 111 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 112 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 113 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 114 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 115 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 116 #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 117 #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 118 #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 120 #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 121 #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 122 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) 123 124 #endif /* FSMC_Bank2_3 */ 125 #if defined(FSMC_Bank4) 126 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) 127 128 #endif /* FSMC_Bank4 */ 129 130 /** 131 * @} 132 */ 133 134 /* Exported typedef ----------------------------------------------------------*/ 135 136 /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types 137 * @{ 138 */ 139 140 #if defined(FSMC_Bank1) 141 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef 142 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef 143 #endif /* FSMC_Bank1 */ 144 #if defined(FSMC_Bank2_3) 145 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef 146 #endif /* FSMC_Bank2_3 */ 147 #if defined(FSMC_Bank4) 148 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef 149 #endif /* FSMC_Bank4 */ 150 151 #if defined(FSMC_Bank1) 152 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 153 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E 154 #endif /* FSMC_Bank1 */ 155 #if defined(FSMC_Bank2_3) 156 #define FSMC_NAND_DEVICE FSMC_Bank2_3 157 #endif /* FSMC_Bank2_3 */ 158 #if defined(FSMC_Bank4) 159 #define FSMC_PCCARD_DEVICE FSMC_Bank4 160 #endif /* FSMC_Bank4 */ 161 162 #if defined(FSMC_Bank1) 163 /** 164 * @brief FSMC NORSRAM Configuration Structure definition 165 */ 166 typedef struct 167 { 168 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 169 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 170 171 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 172 multiplexed on the data bus or not. 173 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ 174 175 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 176 the corresponding memory device. 177 This parameter can be a value of @ref FSMC_Memory_Type */ 178 179 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 180 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ 181 182 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 183 valid only with synchronous burst Flash memories. 184 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 185 186 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 187 the Flash memory in burst mode. 188 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 189 190 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 191 memory, valid only when accessing Flash memories in burst mode. 192 This parameter can be a value of @ref FSMC_Wrap_Mode 193 This mode is available only for the STM32F405/407/4015/417xx devices */ 194 195 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 196 clock cycle before the wait state or during the wait state, 197 valid only when accessing memories in burst mode. 198 This parameter can be a value of @ref FSMC_Wait_Timing */ 199 200 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. 201 This parameter can be a value of @ref FSMC_Write_Operation */ 202 203 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 204 signal, valid for Flash memory access in burst mode. 205 This parameter can be a value of @ref FSMC_Wait_Signal */ 206 207 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 208 This parameter can be a value of @ref FSMC_Extended_Mode */ 209 210 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 211 valid only with asynchronous Flash memories. 212 This parameter can be a value of @ref FSMC_AsynchronousWait */ 213 214 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 215 This parameter can be a value of @ref FSMC_Write_Burst */ 216 217 uint32_t ContinuousClock; /*!< Enables or disables the FSMC clock output to external memory devices. 218 This parameter is only enabled through the FSMC_BCR1 register, 219 and don't care through FSMC_BCR2..4 registers. 220 This parameter can be a value of @ref FSMC_Continous_Clock 221 This mode is available only for the STM32F412Vx/Zx/Rx devices */ 222 223 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FSMC controller. 224 This parameter is only enabled through the FSMC_BCR1 register, 225 and don't care through FSMC_BCR2..4 registers. 226 This parameter can be a value of @ref FSMC_Write_FIFO 227 This mode is available only for the STM32F412Vx/Vx devices */ 228 229 uint32_t PageSize; /*!< Specifies the memory page size. 230 This parameter can be a value of @ref FSMC_Page_Size */ 231 } FSMC_NORSRAM_InitTypeDef; 232 233 /** 234 * @brief FSMC NORSRAM Timing parameters structure definition 235 */ 236 typedef struct 237 { 238 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 239 the duration of the address setup time. 240 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 241 @note This parameter is not used with synchronous NOR Flash memories. */ 242 243 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 244 the duration of the address hold time. 245 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 246 @note This parameter is not used with synchronous NOR Flash memories. */ 247 248 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 249 the duration of the data setup time. 250 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 251 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 252 NOR Flash memories. */ 253 254 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 255 the duration of the bus turnaround. 256 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 257 @note This parameter is only used for multiplexed NOR Flash memories. */ 258 259 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 260 HCLK cycles. This parameter can be a value between Min_Data = 2 and 261 Max_Data = 16. 262 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 263 accesses. */ 264 265 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 266 to the memory before getting the first data. 267 The parameter value depends on the memory type as shown below: 268 - It must be set to 0 in case of a CRAM 269 - It is don't care in asynchronous NOR, SRAM or ROM accesses 270 - It may assume a value between Min_Data = 2 and Max_Data = 17 271 in NOR Flash memories with synchronous burst mode enable */ 272 273 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 274 This parameter can be a value of @ref FSMC_Access_Mode */ 275 } FSMC_NORSRAM_TimingTypeDef; 276 #endif /* FSMC_Bank1 */ 277 278 #if defined(FSMC_Bank2_3) 279 /** 280 * @brief FSMC NAND Configuration Structure definition 281 */ 282 typedef struct 283 { 284 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 285 This parameter can be a value of @ref FSMC_NAND_Bank */ 286 287 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 288 This parameter can be any value of @ref FSMC_Wait_feature */ 289 290 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 291 This parameter can be any value of @ref FSMC_NAND_Data_Width */ 292 293 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 294 This parameter can be any value of @ref FSMC_ECC */ 295 296 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 297 This parameter can be any value of @ref FSMC_ECC_Page_Size */ 298 299 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 300 delay between CLE low and RE low. 301 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 302 303 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 304 delay between ALE low and RE low. 305 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 306 } FSMC_NAND_InitTypeDef; 307 #endif 308 309 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) 310 /** 311 * @brief FSMC NAND Timing parameters structure definition 312 */ 313 typedef struct 314 { 315 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 316 the command assertion for NAND-Flash read or write access 317 to common/Attribute or I/O memory space (depending on 318 the memory space timing to be configured). 319 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 320 321 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 322 command for NAND-Flash read or write access to 323 common/Attribute or I/O memory space (depending on the 324 memory space timing to be configured). 325 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 326 327 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 328 (and data for write access) after the command de-assertion 329 for NAND-Flash read or write access to common/Attribute 330 or I/O memory space (depending on the memory space timing 331 to be configured). 332 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 333 334 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 335 data bus is kept in HiZ after the start of a NAND-Flash 336 write access to common/Attribute or I/O memory space (depending 337 on the memory space timing to be configured). 338 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 339 } FSMC_NAND_PCC_TimingTypeDef; 340 #endif /* FSMC_Bank2_3 */ 341 342 #if defined(FSMC_Bank4) 343 /** 344 * @brief FSMC PCCARD Configuration Structure definition 345 */ 346 typedef struct 347 { 348 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. 349 This parameter can be any value of @ref FSMC_Wait_feature */ 350 351 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 352 delay between CLE low and RE low. 353 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 354 355 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 356 delay between ALE low and RE low. 357 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 358 }FSMC_PCCARD_InitTypeDef; 359 #endif /* FSMC_Bank4 */ 360 361 /** 362 * @} 363 */ 364 365 /* Exported constants --------------------------------------------------------*/ 366 /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants 367 * @{ 368 */ 369 #if defined(FSMC_Bank1) 370 371 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller 372 * @{ 373 */ 374 375 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank 376 * @{ 377 */ 378 #define FSMC_NORSRAM_BANK1 (0x00000000U) 379 #define FSMC_NORSRAM_BANK2 (0x00000002U) 380 #define FSMC_NORSRAM_BANK3 (0x00000004U) 381 #define FSMC_NORSRAM_BANK4 (0x00000006U) 382 /** 383 * @} 384 */ 385 386 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing 387 * @{ 388 */ 389 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 390 #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 391 /** 392 * @} 393 */ 394 395 /** @defgroup FSMC_Memory_Type FSMC Memory Type 396 * @{ 397 */ 398 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) 399 #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) 400 #define FSMC_MEMORY_TYPE_NOR (0x00000008U) 401 /** 402 * @} 403 */ 404 405 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width 406 * @{ 407 */ 408 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 409 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 410 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 411 /** 412 * @} 413 */ 414 415 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access 416 * @{ 417 */ 418 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 419 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 420 /** 421 * @} 422 */ 423 424 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode 425 * @{ 426 */ 427 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 428 #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 429 /** 430 * @} 431 */ 432 433 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity 434 * @{ 435 */ 436 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 437 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 438 /** 439 * @} 440 */ 441 442 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 443 * @note These values are available only for the STM32F405/415/407/417xx devices. 444 * @{ 445 */ 446 #define FSMC_WRAP_MODE_DISABLE (0x00000000U) 447 #define FSMC_WRAP_MODE_ENABLE (0x00000400U) 448 /** 449 * @} 450 */ 451 452 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing 453 * @{ 454 */ 455 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 456 #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) 457 /** 458 * @} 459 */ 460 461 /** @defgroup FSMC_Write_Operation FSMC Write Operation 462 * @{ 463 */ 464 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) 465 #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) 466 /** 467 * @} 468 */ 469 470 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal 471 * @{ 472 */ 473 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) 474 #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) 475 /** 476 * @} 477 */ 478 479 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode 480 * @{ 481 */ 482 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) 483 #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) 484 /** 485 * @} 486 */ 487 488 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait 489 * @{ 490 */ 491 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 492 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 493 /** 494 * @} 495 */ 496 497 /** @defgroup FSMC_Page_Size FSMC Page Size 498 * @{ 499 */ 500 #define FSMC_PAGE_SIZE_NONE (0x00000000U) 501 #define FSMC_PAGE_SIZE_128 FSMC_BCR1_CPSIZE_0 502 #define FSMC_PAGE_SIZE_256 FSMC_BCR1_CPSIZE_1 503 #define FSMC_PAGE_SIZE_512 (FSMC_BCR1_CPSIZE_0\ 504 | FSMC_BCR1_CPSIZE_1) 505 #define FSMC_PAGE_SIZE_1024 FSMC_BCR1_CPSIZE_2 506 /** 507 * @} 508 */ 509 510 /** @defgroup FSMC_Write_Burst FSMC Write Burst 511 * @{ 512 */ 513 #define FSMC_WRITE_BURST_DISABLE (0x00000000U) 514 #define FSMC_WRITE_BURST_ENABLE (0x00080000U) 515 /** 516 * @} 517 */ 518 519 /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock 520 * @note These values are available only for the STM32F412Vx/Zx/Rx devices. 521 * @{ 522 */ 523 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 524 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 525 /** 526 * @} 527 */ 528 529 #if defined(FSMC_BCR1_WFDIS) 530 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO 531 * @note These values are available only for the STM32F412Vx/Zx/Rx devices. 532 * @{ 533 */ 534 #define FSMC_WRITE_FIFO_DISABLE FSMC_BCR1_WFDIS 535 #define FSMC_WRITE_FIFO_ENABLE (0x00000000U) 536 #endif /* FSMC_BCR1_WFDIS */ 537 /** 538 * @} 539 */ 540 541 /** @defgroup FSMC_Access_Mode FSMC Access Mode 542 * @{ 543 */ 544 #define FSMC_ACCESS_MODE_A (0x00000000U) 545 #define FSMC_ACCESS_MODE_B (0x10000000U) 546 #define FSMC_ACCESS_MODE_C (0x20000000U) 547 #define FSMC_ACCESS_MODE_D (0x30000000U) 548 /** 549 * @} 550 */ 551 552 /** 553 * @} 554 */ 555 #endif /* FSMC_Bank1 */ 556 557 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) 558 559 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller 560 * @{ 561 */ 562 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank 563 * @{ 564 */ 565 #if defined(FSMC_Bank2_3) 566 #define FSMC_NAND_BANK2 (0x00000010U) 567 #endif 568 #define FSMC_NAND_BANK3 (0x00000100U) 569 /** 570 * @} 571 */ 572 573 /** @defgroup FSMC_Wait_feature FSMC Wait feature 574 * @{ 575 */ 576 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) 577 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) 578 /** 579 * @} 580 */ 581 582 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type 583 * @{ 584 */ 585 #if defined(FSMC_Bank4) 586 #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) 587 #endif /* FSMC_Bank4 */ 588 #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 589 /** 590 * @} 591 */ 592 593 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width 594 * @{ 595 */ 596 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) 597 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) 598 /** 599 * @} 600 */ 601 602 /** @defgroup FSMC_ECC FSMC ECC 603 * @{ 604 */ 605 #define FSMC_NAND_ECC_DISABLE (0x00000000U) 606 #define FSMC_NAND_ECC_ENABLE (0x00000040U) 607 /** 608 * @} 609 */ 610 611 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size 612 * @{ 613 */ 614 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 615 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 616 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 617 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 618 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 619 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 620 /** 621 * @} 622 */ 623 624 /** 625 * @} 626 */ 627 #endif /* FSMC_Bank2_3 || FSMC_Bank4 */ 628 629 630 /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition 631 * @{ 632 */ 633 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) 634 #define FSMC_IT_RISING_EDGE (0x00000008U) 635 #define FSMC_IT_LEVEL (0x00000010U) 636 #define FSMC_IT_FALLING_EDGE (0x00000020U) 637 #endif /* FSMC_Bank2_3 || FSMC_Bank4 */ 638 /** 639 * @} 640 */ 641 642 /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition 643 * @{ 644 */ 645 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) 646 #define FSMC_FLAG_RISING_EDGE (0x00000001U) 647 #define FSMC_FLAG_LEVEL (0x00000002U) 648 #define FSMC_FLAG_FALLING_EDGE (0x00000004U) 649 #define FSMC_FLAG_FEMPT (0x00000040U) 650 #endif /* FSMC_Bank2_3 || FSMC_Bank4 */ 651 /** 652 * @} 653 */ 654 655 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition 656 * @{ 657 */ 658 #define FMC_WRITE_OPERATION_DISABLE FSMC_WRITE_OPERATION_DISABLE 659 #define FMC_WRITE_OPERATION_ENABLE FSMC_WRITE_OPERATION_ENABLE 660 661 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 662 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 663 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32 664 665 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef 666 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef 667 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef 668 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef 669 670 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init 671 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init 672 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init 673 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit 674 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable 675 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable 676 677 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE 678 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE 679 680 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) 681 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef 682 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef 683 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef 684 685 #define FMC_NAND_Init FSMC_NAND_Init 686 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init 687 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init 688 #define FMC_NAND_DeInit FSMC_NAND_DeInit 689 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable 690 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable 691 #define FMC_NAND_GetECC FSMC_NAND_GetECC 692 #define FMC_PCCARD_Init FSMC_PCCARD_Init 693 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init 694 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init 695 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init 696 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit 697 698 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE 699 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE 700 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE 701 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE 702 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT 703 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT 704 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG 705 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG 706 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT 707 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT 708 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG 709 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG 710 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 711 712 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef 713 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef 714 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) 715 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef 716 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef 717 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 718 719 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE 720 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE 721 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) 722 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE 723 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE 724 725 #define FMC_NAND_BANK2 FSMC_NAND_BANK2 726 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 727 728 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 729 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 730 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 731 732 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE 733 #define FMC_IT_LEVEL FSMC_IT_LEVEL 734 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE 735 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR 736 737 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE 738 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL 739 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE 740 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT 741 /** 742 * @} 743 */ 744 745 /** 746 * @} 747 */ 748 749 /** 750 * @} 751 */ 752 753 /* Private macro -------------------------------------------------------------*/ 754 /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros 755 * @{ 756 */ 757 #if defined(FSMC_Bank1) 758 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros 759 * @brief macros to handle NOR device enable/disable and read/write operations 760 * @{ 761 */ 762 763 /** 764 * @brief Enable the NORSRAM device access. 765 * @param __INSTANCE__ FSMC_NORSRAM Instance 766 * @param __BANK__ FSMC_NORSRAM Bank 767 * @retval None 768 */ 769 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 770 |= FSMC_BCR1_MBKEN) 771 772 /** 773 * @brief Disable the NORSRAM device access. 774 * @param __INSTANCE__ FSMC_NORSRAM Instance 775 * @param __BANK__ FSMC_NORSRAM Bank 776 * @retval None 777 */ 778 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 779 &= ~FSMC_BCR1_MBKEN) 780 781 /** 782 * @} 783 */ 784 #endif /* FSMC_Bank1 */ 785 786 #if defined(FSMC_Bank2_3) 787 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros 788 * @brief macros to handle NAND device enable/disable 789 * @{ 790 */ 791 792 /** 793 * @brief Enable the NAND device access. 794 * @param __INSTANCE__ FSMC_NAND Instance 795 * @param __BANK__ FSMC_NAND Bank 796 * @retval None 797 */ 798 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ 799 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) 800 801 /** 802 * @brief Disable the NAND device access. 803 * @param __INSTANCE__ FSMC_NAND Instance 804 * @param __BANK__ FSMC_NAND Bank 805 * @retval None 806 */ 807 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \ 808 CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) 809 810 /** 811 * @} 812 */ 813 #endif /* FSMC_Bank2_3 */ 814 815 #if defined(FSMC_Bank4) 816 /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros 817 * @brief macros to handle PCCARD read/write operations 818 * @{ 819 */ 820 /** 821 * @brief Enable the PCCARD device access. 822 * @param __INSTANCE__ FSMC_PCCARD Instance 823 * @retval None 824 */ 825 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) 826 827 /** 828 * @brief Disable the PCCARD device access. 829 * @param __INSTANCE__ FSMC_PCCARD Instance 830 * @retval None 831 */ 832 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) 833 /** 834 * @} 835 */ 836 837 #endif 838 #if defined(FSMC_Bank2_3) 839 /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt 840 * @brief macros to handle NAND interrupts 841 * @{ 842 */ 843 844 /** 845 * @brief Enable the NAND device interrupt. 846 * @param __INSTANCE__ FSMC_NAND instance 847 * @param __BANK__ FSMC_NAND Bank 848 * @param __INTERRUPT__ FSMC_NAND interrupt 849 * This parameter can be any combination of the following values: 850 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 851 * @arg FSMC_IT_LEVEL: Interrupt level. 852 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 853 * @retval None 854 */ 855 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ 856 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) 857 858 /** 859 * @brief Disable the NAND device interrupt. 860 * @param __INSTANCE__ FSMC_NAND Instance 861 * @param __BANK__ FSMC_NAND Bank 862 * @param __INTERRUPT__ FSMC_NAND interrupt 863 * This parameter can be any combination of the following values: 864 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 865 * @arg FSMC_IT_LEVEL: Interrupt level. 866 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 867 * @retval None 868 */ 869 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ 870 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 871 872 /** 873 * @brief Get flag status of the NAND device. 874 * @param __INSTANCE__ FSMC_NAND Instance 875 * @param __BANK__ FSMC_NAND Bank 876 * @param __FLAG__ FSMC_NAND flag 877 * This parameter can be any combination of the following values: 878 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 879 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 880 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 881 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 882 * @retval The state of FLAG (SET or RESET). 883 */ 884 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ 885 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) 886 887 /** 888 * @brief Clear flag status of the NAND device. 889 * @param __INSTANCE__ FSMC_NAND Instance 890 * @param __BANK__ FSMC_NAND Bank 891 * @param __FLAG__ FSMC_NAND flag 892 * This parameter can be any combination of the following values: 893 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 894 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 895 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 896 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 897 * @retval None 898 */ 899 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ 900 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 901 902 /** 903 * @} 904 */ 905 #endif /* FSMC_Bank2_3 */ 906 907 #if defined(FSMC_Bank4) 908 /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt 909 * @brief macros to handle PCCARD interrupts 910 * @{ 911 */ 912 913 /** 914 * @brief Enable the PCCARD device interrupt. 915 * @param __INSTANCE__ FSMC_PCCARD instance 916 * @param __INTERRUPT__ FSMC_PCCARD interrupt 917 * This parameter can be any combination of the following values: 918 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 919 * @arg FSMC_IT_LEVEL: Interrupt level. 920 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 921 * @retval None 922 */ 923 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) 924 925 /** 926 * @brief Disable the PCCARD device interrupt. 927 * @param __INSTANCE__ FSMC_PCCARD instance 928 * @param __INTERRUPT__ FSMC_PCCARD interrupt 929 * This parameter can be any combination of the following values: 930 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 931 * @arg FSMC_IT_LEVEL: Interrupt level. 932 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 933 * @retval None 934 */ 935 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 936 937 /** 938 * @brief Get flag status of the PCCARD device. 939 * @param __INSTANCE__ FSMC_PCCARD instance 940 * @param __FLAG__ FSMC_PCCARD flag 941 * This parameter can be any combination of the following values: 942 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 943 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 944 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 945 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 946 * @retval The state of FLAG (SET or RESET). 947 */ 948 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) 949 950 /** 951 * @brief Clear flag status of the PCCARD device. 952 * @param __INSTANCE__ FSMC_PCCARD instance 953 * @param __FLAG__ FSMC_PCCARD flag 954 * This parameter can be any combination of the following values: 955 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 956 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 957 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 958 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 959 * @retval None 960 */ 961 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) 962 963 /** 964 * @} 965 */ 966 #endif 967 968 /** 969 * @} 970 */ 971 972 /** 973 * @} 974 */ 975 976 /* Private functions ---------------------------------------------------------*/ 977 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions 978 * @{ 979 */ 980 981 #if defined(FSMC_Bank1) 982 /** @defgroup FSMC_LL_NORSRAM NOR SRAM 983 * @{ 984 */ 985 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 986 * @{ 987 */ 988 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, 989 FSMC_NORSRAM_InitTypeDef *Init); 990 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, 991 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 992 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, 993 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 994 uint32_t ExtendedMode); 995 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, 996 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 997 /** 998 * @} 999 */ 1000 1001 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1002 * @{ 1003 */ 1004 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1005 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1006 /** 1007 * @} 1008 */ 1009 /** 1010 * @} 1011 */ 1012 #endif /* FSMC_Bank1 */ 1013 1014 #if defined(FSMC_Bank2_3) 1015 /** @defgroup FSMC_LL_NAND NAND 1016 * @{ 1017 */ 1018 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1019 * @{ 1020 */ 1021 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); 1022 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 1023 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1024 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 1025 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1026 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1032 * @{ 1033 */ 1034 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 1035 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 1036 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 1037 uint32_t Timeout); 1038 /** 1039 * @} 1040 */ 1041 /** 1042 * @} 1043 */ 1044 #endif /* FSMC_Bank2_3 */ 1045 1046 #if defined(FSMC_Bank4) 1047 /** @defgroup FSMC_LL_PCCARD PCCARD 1048 * @{ 1049 */ 1050 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 1051 * @{ 1052 */ 1053 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); 1054 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 1055 FSMC_NAND_PCC_TimingTypeDef *Timing); 1056 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 1057 FSMC_NAND_PCC_TimingTypeDef *Timing); 1058 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 1059 FSMC_NAND_PCC_TimingTypeDef *Timing); 1060 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); 1061 /** 1062 * @} 1063 */ 1064 /** 1065 * @} 1066 */ 1067 #endif /* FSMC_Bank4 */ 1068 1069 1070 /** 1071 * @} 1072 */ 1073 1074 /** 1075 * @} 1076 */ 1077 1078 /** 1079 * @} 1080 */ 1081 1082 #ifdef __cplusplus 1083 } 1084 #endif 1085 1086 #endif /* STM32F4xx_LL_FSMC_H */ 1087
