1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_LL_FMC_H 21 #define STM32H7xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK4)) 46 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 51 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 54 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 55 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 59 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 60 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 61 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 62 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 63 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 64 ((__MODE__) == FMC_ACCESS_MODE_D)) 65 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 66 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 67 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 68 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 69 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 70 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 71 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 72 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 73 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 74 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 75 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 76 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 77 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 78 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 79 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 80 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 81 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 82 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 83 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 84 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 85 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 86 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 87 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 88 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 89 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 90 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 91 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 92 93 94 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 95 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 96 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 97 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 98 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 99 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 100 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 101 102 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 103 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 104 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 105 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 106 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 107 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 108 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 109 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 110 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 111 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 112 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 113 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 114 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 115 116 117 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ 118 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ 119 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) 120 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ 121 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 122 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ 123 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ 124 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 125 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ 126 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 127 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ 128 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ 129 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 130 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ 131 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ 132 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ 133 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ 134 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ 135 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ 136 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 137 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ 138 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ 139 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 140 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 141 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 142 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 143 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 144 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 145 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 146 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 147 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) 148 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) 149 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) 150 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 151 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ 152 ((__BANK__) == FMC_SDRAM_BANK2)) 153 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ 154 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ 155 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ 156 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 157 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ 158 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ 159 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) 160 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ 161 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 162 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ 163 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ 164 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) 165 166 167 /** 168 * @} 169 */ 170 171 /* Exported typedef ----------------------------------------------------------*/ 172 173 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 174 * @{ 175 */ 176 177 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 178 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 179 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 180 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 181 182 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 183 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 184 #define FMC_NAND_DEVICE FMC_Bank3_R 185 #define FMC_SDRAM_DEVICE FMC_Bank5_6_R 186 187 /** 188 * @brief FMC NORSRAM Configuration Structure definition 189 */ 190 typedef struct 191 { 192 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 193 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 194 195 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 196 multiplexed on the data bus or not. 197 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 198 199 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 200 the corresponding memory device. 201 This parameter can be a value of @ref FMC_Memory_Type */ 202 203 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 204 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 205 206 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 207 valid only with synchronous burst Flash memories. 208 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 209 210 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 211 the Flash memory in burst mode. 212 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 213 214 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 215 clock cycle before the wait state or during the wait state, 216 valid only when accessing memories in burst mode. 217 This parameter can be a value of @ref FMC_Wait_Timing */ 218 219 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 220 This parameter can be a value of @ref FMC_Write_Operation */ 221 222 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 223 signal, valid for Flash memory access in burst mode. 224 This parameter can be a value of @ref FMC_Wait_Signal */ 225 226 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 227 This parameter can be a value of @ref FMC_Extended_Mode */ 228 229 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 230 valid only with asynchronous Flash memories. 231 This parameter can be a value of @ref FMC_AsynchronousWait */ 232 233 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 234 This parameter can be a value of @ref FMC_Write_Burst */ 235 236 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 237 This parameter is only enabled through the FMC_BCR1 register, 238 and don't care through FMC_BCR2..4 registers. 239 This parameter can be a value of @ref FMC_Continous_Clock */ 240 241 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 242 This parameter is only enabled through the FMC_BCR1 register, 243 and don't care through FMC_BCR2..4 registers. 244 This parameter can be a value of @ref FMC_Write_FIFO */ 245 246 uint32_t PageSize; /*!< Specifies the memory page size. 247 This parameter can be a value of @ref FMC_Page_Size */ 248 } FMC_NORSRAM_InitTypeDef; 249 250 /** 251 * @brief FMC NORSRAM Timing parameters structure definition 252 */ 253 typedef struct 254 { 255 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 256 the duration of the address setup time. 257 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 258 @note This parameter is not used with synchronous NOR Flash memories. */ 259 260 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 261 the duration of the address hold time. 262 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 263 @note This parameter is not used with synchronous NOR Flash memories. */ 264 265 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 266 the duration of the data setup time. 267 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 268 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 269 NOR Flash memories. */ 270 271 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 272 the duration of the bus turnaround. 273 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 274 @note This parameter is only used for multiplexed NOR Flash memories. */ 275 276 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 277 HCLK cycles. This parameter can be a value between Min_Data = 2 and 278 Max_Data = 16. 279 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 280 accesses. */ 281 282 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 283 to the memory before getting the first data. 284 The parameter value depends on the memory type as shown below: 285 - It must be set to 0 in case of a CRAM 286 - It is don't care in asynchronous NOR, SRAM or ROM accesses 287 - It may assume a value between Min_Data = 2 and Max_Data = 17 288 in NOR Flash memories with synchronous burst mode enable */ 289 290 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 291 This parameter can be a value of @ref FMC_Access_Mode */ 292 } FMC_NORSRAM_TimingTypeDef; 293 294 /** 295 * @brief FMC NAND Configuration Structure definition 296 */ 297 typedef struct 298 { 299 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 300 This parameter can be a value of @ref FMC_NAND_Bank */ 301 302 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 303 This parameter can be any value of @ref FMC_Wait_feature */ 304 305 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 306 This parameter can be any value of @ref FMC_NAND_Data_Width */ 307 308 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 309 This parameter can be any value of @ref FMC_ECC */ 310 311 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 312 This parameter can be any value of @ref FMC_ECC_Page_Size */ 313 314 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 315 delay between CLE low and RE low. 316 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 317 318 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 319 delay between ALE low and RE low. 320 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 321 } FMC_NAND_InitTypeDef; 322 323 /** 324 * @brief FMC NAND Timing parameters structure definition 325 */ 326 typedef struct 327 { 328 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 329 the command assertion for NAND-Flash read or write access 330 to common/Attribute or I/O memory space (depending on 331 the memory space timing to be configured). 332 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 333 334 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 335 command for NAND-Flash read or write access to 336 common/Attribute or I/O memory space (depending on the 337 memory space timing to be configured). 338 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 339 340 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 341 (and data for write access) after the command de-assertion 342 for NAND-Flash read or write access to common/Attribute 343 or I/O memory space (depending on the memory space timing 344 to be configured). 345 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 346 347 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 348 data bus is kept in HiZ after the start of a NAND-Flash 349 write access to common/Attribute or I/O memory space (depending 350 on the memory space timing to be configured). 351 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 352 } FMC_NAND_PCC_TimingTypeDef; 353 354 355 /** 356 * @brief FMC SDRAM Configuration Structure definition 357 */ 358 typedef struct 359 { 360 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. 361 This parameter can be a value of @ref FMC_SDRAM_Bank */ 362 363 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. 364 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ 365 366 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. 367 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ 368 369 uint32_t MemoryDataWidth; /*!< Defines the memory device width. 370 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ 371 372 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. 373 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ 374 375 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. 376 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ 377 378 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. 379 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ 380 381 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 382 to disable the clock before changing frequency. 383 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ 384 385 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read 386 commands during the CAS latency and stores data in the Read FIFO. 387 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ 388 389 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. 390 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ 391 } FMC_SDRAM_InitTypeDef; 392 393 /** 394 * @brief FMC SDRAM Timing parameters structure definition 395 */ 396 typedef struct 397 { 398 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and 399 an active or Refresh command in number of memory clock cycles. 400 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 401 402 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to 403 issuing the Activate command in number of memory clock cycles. 404 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 405 406 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock 407 cycles. 408 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 409 410 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command 411 and the delay between two consecutive Refresh commands in number of 412 memory clock cycles. 413 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 414 415 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. 416 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 417 418 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command 419 in number of memory clock cycles. 420 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 421 422 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write 423 command in number of memory clock cycles. 424 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 425 } FMC_SDRAM_TimingTypeDef; 426 427 /** 428 * @brief SDRAM command parameters structure definition 429 */ 430 typedef struct 431 { 432 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. 433 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ 434 435 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. 436 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ 437 438 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued 439 in auto refresh mode. 440 This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ 441 442 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ 443 } FMC_SDRAM_CommandTypeDef; 444 /** 445 * @} 446 */ 447 448 /* Exported constants --------------------------------------------------------*/ 449 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 450 * @{ 451 */ 452 453 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 454 * @{ 455 */ 456 457 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 458 * @{ 459 */ 460 #define FMC_NORSRAM_BANK1 (0x00000000U) 461 #define FMC_NORSRAM_BANK2 (0x00000002U) 462 #define FMC_NORSRAM_BANK3 (0x00000004U) 463 #define FMC_NORSRAM_BANK4 (0x00000006U) 464 /** 465 * @} 466 */ 467 468 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 469 * @{ 470 */ 471 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 472 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 473 /** 474 * @} 475 */ 476 477 /** @defgroup FMC_Memory_Type FMC Memory Type 478 * @{ 479 */ 480 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 481 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 482 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 483 /** 484 * @} 485 */ 486 487 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 488 * @{ 489 */ 490 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 491 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 492 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 493 /** 494 * @} 495 */ 496 497 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 498 * @{ 499 */ 500 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 501 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 502 /** 503 * @} 504 */ 505 506 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 507 * @{ 508 */ 509 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 510 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 511 /** 512 * @} 513 */ 514 515 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 516 * @{ 517 */ 518 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 519 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 520 /** 521 * @} 522 */ 523 524 /** @defgroup FMC_Wait_Timing FMC Wait Timing 525 * @{ 526 */ 527 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 528 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 529 /** 530 * @} 531 */ 532 533 /** @defgroup FMC_Write_Operation FMC Write Operation 534 * @{ 535 */ 536 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 537 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 538 /** 539 * @} 540 */ 541 542 /** @defgroup FMC_Wait_Signal FMC Wait Signal 543 * @{ 544 */ 545 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 546 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 547 /** 548 * @} 549 */ 550 551 /** @defgroup FMC_Extended_Mode FMC Extended Mode 552 * @{ 553 */ 554 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 555 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 556 /** 557 * @} 558 */ 559 560 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 561 * @{ 562 */ 563 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 564 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 565 /** 566 * @} 567 */ 568 569 /** @defgroup FMC_Page_Size FMC Page Size 570 * @{ 571 */ 572 #define FMC_PAGE_SIZE_NONE (0x00000000U) 573 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 574 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 575 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 576 | FMC_BCRx_CPSIZE_1) 577 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 578 /** 579 * @} 580 */ 581 582 /** @defgroup FMC_Write_Burst FMC Write Burst 583 * @{ 584 */ 585 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 586 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 587 /** 588 * @} 589 */ 590 591 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 592 * @{ 593 */ 594 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 595 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 596 /** 597 * @} 598 */ 599 600 #if defined(FMC_BCR1_WFDIS) 601 /** @defgroup FMC_Write_FIFO FMC Write FIFO 602 * @{ 603 */ 604 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 605 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 606 #endif /* FMC_BCR1_WFDIS */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup FMC_Access_Mode FMC Access Mode 612 * @{ 613 */ 614 #define FMC_ACCESS_MODE_A (0x00000000U) 615 #define FMC_ACCESS_MODE_B (0x10000000U) 616 #define FMC_ACCESS_MODE_C (0x20000000U) 617 #define FMC_ACCESS_MODE_D (0x30000000U) 618 /** 619 * @} 620 */ 621 622 /** 623 * @} 624 */ 625 626 627 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 628 * @{ 629 */ 630 /** @defgroup FMC_NAND_Bank FMC NAND Bank 631 * @{ 632 */ 633 #define FMC_NAND_BANK3 (0x00000100U) 634 /** 635 * @} 636 */ 637 638 /** @defgroup FMC_Wait_feature FMC Wait feature 639 * @{ 640 */ 641 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 642 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 643 /** 644 * @} 645 */ 646 647 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 648 * @{ 649 */ 650 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 651 /** 652 * @} 653 */ 654 655 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 656 * @{ 657 */ 658 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 659 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 660 /** 661 * @} 662 */ 663 664 /** @defgroup FMC_ECC FMC ECC 665 * @{ 666 */ 667 #define FMC_NAND_ECC_DISABLE (0x00000000U) 668 #define FMC_NAND_ECC_ENABLE (0x00000040U) 669 /** 670 * @} 671 */ 672 673 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 674 * @{ 675 */ 676 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 677 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 678 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 679 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 680 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 681 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 682 /** 683 * @} 684 */ 685 686 /** 687 * @} 688 */ 689 690 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 691 * @{ 692 */ 693 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank 694 * @{ 695 */ 696 #define FMC_SDRAM_BANK1 (0x00000000U) 697 #define FMC_SDRAM_BANK2 (0x00000001U) 698 /** 699 * @} 700 */ 701 702 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 703 * @{ 704 */ 705 #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) 706 #define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) 707 #define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) 708 #define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) 709 /** 710 * @} 711 */ 712 713 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number 714 * @{ 715 */ 716 #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) 717 #define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) 718 #define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) 719 /** 720 * @} 721 */ 722 723 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width 724 * @{ 725 */ 726 #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) 727 #define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) 728 #define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) 729 /** 730 * @} 731 */ 732 733 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number 734 * @{ 735 */ 736 #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) 737 #define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) 738 /** 739 * @} 740 */ 741 742 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency 743 * @{ 744 */ 745 #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) 746 #define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) 747 #define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) 748 /** 749 * @} 750 */ 751 752 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection 753 * @{ 754 */ 755 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) 756 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) 757 /** 758 * @} 759 */ 760 761 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period 762 * @{ 763 */ 764 #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) 765 #define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) 766 #define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) 767 /** 768 * @} 769 */ 770 771 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst 772 * @{ 773 */ 774 #define FMC_SDRAM_RBURST_DISABLE (0x00000000U) 775 #define FMC_SDRAM_RBURST_ENABLE (0x00001000U) 776 /** 777 * @} 778 */ 779 780 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay 781 * @{ 782 */ 783 #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) 784 #define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) 785 #define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) 786 /** 787 * @} 788 */ 789 790 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode 791 * @{ 792 */ 793 #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) 794 #define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) 795 #define FMC_SDRAM_CMD_PALL (0x00000002U) 796 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) 797 #define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) 798 #define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) 799 #define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) 800 /** 801 * @} 802 */ 803 804 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target 805 * @{ 806 */ 807 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 808 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 809 #define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) 810 /** 811 * @} 812 */ 813 814 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 815 * @{ 816 */ 817 #define FMC_SDRAM_NORMAL_MODE (0x00000000U) 818 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 819 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 820 /** 821 * @} 822 */ 823 824 /** 825 * @} 826 */ 827 828 829 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 830 * @{ 831 */ 832 #define FMC_IT_RISING_EDGE (0x00000008U) 833 #define FMC_IT_LEVEL (0x00000010U) 834 #define FMC_IT_FALLING_EDGE (0x00000020U) 835 #define FMC_IT_REFRESH_ERROR (0x00004000U) 836 /** 837 * @} 838 */ 839 840 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 841 * @{ 842 */ 843 #define FMC_FLAG_RISING_EDGE (0x00000001U) 844 #define FMC_FLAG_LEVEL (0x00000002U) 845 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 846 #define FMC_FLAG_FEMPT (0x00000040U) 847 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 848 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 849 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 850 /** 851 * @} 852 */ 853 854 /** 855 * @} 856 */ 857 858 /** 859 * @} 860 */ 861 862 /* Private macro -------------------------------------------------------------*/ 863 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 864 * @{ 865 */ 866 /** 867 * @brief Enable the FMC Peripheral. 868 * @retval None 869 */ 870 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) 871 872 /** 873 * @brief Disable the FMC Peripheral. 874 * @retval None 875 */ 876 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) 877 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 878 * @brief macros to handle NOR device enable/disable and read/write operations 879 * @{ 880 */ 881 882 /** 883 * @brief Enable the NORSRAM device access. 884 * @param __INSTANCE__ FMC_NORSRAM Instance 885 * @param __BANK__ FMC_NORSRAM Bank 886 * @retval None 887 */ 888 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 889 |= FMC_BCRx_MBKEN) 890 891 /** 892 * @brief Disable the NORSRAM device access. 893 * @param __INSTANCE__ FMC_NORSRAM Instance 894 * @param __BANK__ FMC_NORSRAM Bank 895 * @retval None 896 */ 897 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 898 &= ~FMC_BCRx_MBKEN) 899 900 /** 901 * @} 902 */ 903 904 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 905 * @brief macros to handle NAND device enable/disable 906 * @{ 907 */ 908 909 /** 910 * @brief Enable the NAND device access. 911 * @param __INSTANCE__ FMC_NAND Instance 912 * @retval None 913 */ 914 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 915 916 /** 917 * @brief Disable the NAND device access. 918 * @param __INSTANCE__ FMC_NAND Instance 919 * @param __BANK__ FMC_NAND Bank 920 * @retval None 921 */ 922 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 923 924 /** 925 * @} 926 */ 927 928 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 929 * @brief macros to handle NAND interrupts 930 * @{ 931 */ 932 933 /** 934 * @brief Enable the NAND device interrupt. 935 * @param __INSTANCE__ FMC_NAND instance 936 * @param __INTERRUPT__ FMC_NAND interrupt 937 * This parameter can be any combination of the following values: 938 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 939 * @arg FMC_IT_LEVEL: Interrupt level. 940 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 941 * @retval None 942 */ 943 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 944 945 /** 946 * @brief Disable the NAND device interrupt. 947 * @param __INSTANCE__ FMC_NAND Instance 948 * @param __INTERRUPT__ FMC_NAND interrupt 949 * This parameter can be any combination of the following values: 950 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 951 * @arg FMC_IT_LEVEL: Interrupt level. 952 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 953 * @retval None 954 */ 955 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 956 957 /** 958 * @brief Get flag status of the NAND device. 959 * @param __INSTANCE__ FMC_NAND Instance 960 * @param __BANK__ FMC_NAND Bank 961 * @param __FLAG__ FMC_NAND flag 962 * This parameter can be any combination of the following values: 963 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 964 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 965 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 966 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 967 * @retval The state of FLAG (SET or RESET). 968 */ 969 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 970 971 /** 972 * @brief Clear flag status of the NAND device. 973 * @param __INSTANCE__ FMC_NAND Instance 974 * @param __FLAG__ FMC_NAND flag 975 * This parameter can be any combination of the following values: 976 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 977 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 978 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 979 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 980 * @retval None 981 */ 982 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 983 984 /** 985 * @} 986 */ 987 988 989 /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt 990 * @brief macros to handle SDRAM interrupts 991 * @{ 992 */ 993 994 /** 995 * @brief Enable the SDRAM device interrupt. 996 * @param __INSTANCE__ FMC_SDRAM instance 997 * @param __INTERRUPT__ FMC_SDRAM interrupt 998 * This parameter can be any combination of the following values: 999 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1000 * @retval None 1001 */ 1002 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 1003 1004 /** 1005 * @brief Disable the SDRAM device interrupt. 1006 * @param __INSTANCE__ FMC_SDRAM instance 1007 * @param __INTERRUPT__ FMC_SDRAM interrupt 1008 * This parameter can be any combination of the following values: 1009 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1010 * @retval None 1011 */ 1012 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 1013 1014 /** 1015 * @brief Get flag status of the SDRAM device. 1016 * @param __INSTANCE__ FMC_SDRAM instance 1017 * @param __FLAG__ FMC_SDRAM flag 1018 * This parameter can be any combination of the following values: 1019 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. 1020 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. 1021 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. 1022 * @retval The state of FLAG (SET or RESET). 1023 */ 1024 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 1025 1026 /** 1027 * @brief Clear flag status of the SDRAM device. 1028 * @param __INSTANCE__ FMC_SDRAM instance 1029 * @param __FLAG__ FMC_SDRAM flag 1030 * This parameter can be any combination of the following values: 1031 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR 1032 * @retval None 1033 */ 1034 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 1035 1036 /** 1037 * @} 1038 */ 1039 /** 1040 * @} 1041 */ 1042 1043 /** 1044 * @} 1045 */ 1046 1047 /* Private functions ---------------------------------------------------------*/ 1048 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 1049 * @{ 1050 */ 1051 1052 /** @defgroup FMC_LL_NORSRAM NOR SRAM 1053 * @{ 1054 */ 1055 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 1056 * @{ 1057 */ 1058 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 1059 FMC_NORSRAM_InitTypeDef *Init); 1060 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 1061 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 1062 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 1063 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 1064 uint32_t ExtendedMode); 1065 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 1066 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 1067 /** 1068 * @} 1069 */ 1070 1071 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1072 * @{ 1073 */ 1074 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1075 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1076 /** 1077 * @} 1078 */ 1079 /** 1080 * @} 1081 */ 1082 1083 /** @defgroup FMC_LL_NAND NAND 1084 * @{ 1085 */ 1086 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1087 * @{ 1088 */ 1089 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 1090 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1091 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1092 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1093 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1094 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 1095 /** 1096 * @} 1097 */ 1098 1099 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1100 * @{ 1101 */ 1102 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1103 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1104 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 1105 uint32_t Timeout); 1106 /** 1107 * @} 1108 */ 1109 /** 1110 * @} 1111 */ 1112 1113 1114 /** @defgroup FMC_LL_SDRAM SDRAM 1115 * @{ 1116 */ 1117 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 1118 * @{ 1119 */ 1120 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); 1121 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, 1122 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); 1123 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1124 /** 1125 * @} 1126 */ 1127 1128 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 1129 * @{ 1130 */ 1131 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1132 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1133 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, 1134 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); 1135 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); 1136 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, 1137 uint32_t AutoRefreshNumber); 1138 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1139 /** 1140 * @} 1141 */ 1142 /** 1143 * @} 1144 */ 1145 1146 /** 1147 * @} 1148 */ 1149 1150 /** 1151 * @} 1152 */ 1153 1154 /** 1155 * @} 1156 */ 1157 1158 #ifdef __cplusplus 1159 } 1160 #endif 1161 1162 #endif /* STM32H7xx_LL_FMC_H */ 1163
