1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_ll_fsmc.h 4 * @author MCD Application Team 5 * @brief Header file of FSMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F2xx_LL_FSMC_H 21 #define STM32F2xx_LL_FSMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f2xx_hal_def.h" 29 30 /** @addtogroup STM32F2xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FSMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FSMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FSMC_NORSRAM_BANK4)) 46 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) 51 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 53 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) 54 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ 55 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ 56 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ 57 ((__MODE__) == FSMC_ACCESS_MODE_D)) 58 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ 59 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) 60 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ 61 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) 62 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ 63 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 64 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ 65 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 66 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ 67 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) 68 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ 69 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 70 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ 71 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) 72 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 73 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) 74 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 75 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ 76 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 77 #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 78 ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 79 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 80 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 81 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 82 #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 83 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 84 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 85 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) 86 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) 87 88 89 #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) 90 #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ 91 ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) 92 #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ 93 ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) 94 #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ 95 ((__STATE__) == FSMC_NAND_ECC_ENABLE)) 96 97 #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 98 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 99 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 100 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 101 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 102 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 103 #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 104 #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 105 #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 106 #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 107 #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 108 #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 109 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) 110 111 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) 112 113 114 /** 115 * @} 116 */ 117 118 /* Exported typedef ----------------------------------------------------------*/ 119 120 /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types 121 * @{ 122 */ 123 124 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef 125 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef 126 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef 127 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef 128 129 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 130 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E 131 #define FSMC_NAND_DEVICE FSMC_Bank2_3 132 #define FSMC_PCCARD_DEVICE FSMC_Bank4 133 134 /** 135 * @brief FSMC NORSRAM Configuration Structure definition 136 */ 137 typedef struct 138 { 139 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 140 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 141 142 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 143 multiplexed on the data bus or not. 144 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ 145 146 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 147 the corresponding memory device. 148 This parameter can be a value of @ref FSMC_Memory_Type */ 149 150 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 151 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ 152 153 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 154 valid only with synchronous burst Flash memories. 155 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 156 157 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 158 the Flash memory in burst mode. 159 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 160 161 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 162 memory, valid only when accessing Flash memories in burst mode. 163 This parameter can be a value of @ref FSMC_Wrap_Mode */ 164 165 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 166 clock cycle before the wait state or during the wait state, 167 valid only when accessing memories in burst mode. 168 This parameter can be a value of @ref FSMC_Wait_Timing */ 169 170 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. 171 This parameter can be a value of @ref FSMC_Write_Operation */ 172 173 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 174 signal, valid for Flash memory access in burst mode. 175 This parameter can be a value of @ref FSMC_Wait_Signal */ 176 177 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 178 This parameter can be a value of @ref FSMC_Extended_Mode */ 179 180 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 181 valid only with asynchronous Flash memories. 182 This parameter can be a value of @ref FSMC_AsynchronousWait */ 183 184 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 185 This parameter can be a value of @ref FSMC_Write_Burst */ 186 187 } FSMC_NORSRAM_InitTypeDef; 188 189 /** 190 * @brief FSMC NORSRAM Timing parameters structure definition 191 */ 192 typedef struct 193 { 194 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 195 the duration of the address setup time. 196 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 197 @note This parameter is not used with synchronous NOR Flash memories. */ 198 199 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 200 the duration of the address hold time. 201 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 202 @note This parameter is not used with synchronous NOR Flash memories. */ 203 204 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 205 the duration of the data setup time. 206 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 207 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 208 NOR Flash memories. */ 209 210 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 211 the duration of the bus turnaround. 212 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 213 @note This parameter is only used for multiplexed NOR Flash memories. */ 214 215 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 216 HCLK cycles. This parameter can be a value between Min_Data = 2 and 217 Max_Data = 16. 218 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 219 accesses. */ 220 221 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 222 to the memory before getting the first data. 223 The parameter value depends on the memory type as shown below: 224 - It must be set to 0 in case of a CRAM 225 - It is don't care in asynchronous NOR, SRAM or ROM accesses 226 - It may assume a value between Min_Data = 2 and Max_Data = 17 227 in NOR Flash memories with synchronous burst mode enable */ 228 229 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 230 This parameter can be a value of @ref FSMC_Access_Mode */ 231 } FSMC_NORSRAM_TimingTypeDef; 232 233 /** 234 * @brief FSMC NAND Configuration Structure definition 235 */ 236 typedef struct 237 { 238 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 239 This parameter can be a value of @ref FSMC_NAND_Bank */ 240 241 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 242 This parameter can be any value of @ref FSMC_Wait_feature */ 243 244 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 245 This parameter can be any value of @ref FSMC_NAND_Data_Width */ 246 247 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 248 This parameter can be any value of @ref FSMC_ECC */ 249 250 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 251 This parameter can be any value of @ref FSMC_ECC_Page_Size */ 252 253 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 254 delay between CLE low and RE low. 255 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 256 257 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 258 delay between ALE low and RE low. 259 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 260 } FSMC_NAND_InitTypeDef; 261 262 /** 263 * @brief FSMC NAND Timing parameters structure definition 264 */ 265 typedef struct 266 { 267 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 268 the command assertion for NAND-Flash read or write access 269 to common/Attribute or I/O memory space (depending on 270 the memory space timing to be configured). 271 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 272 273 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 274 command for NAND-Flash read or write access to 275 common/Attribute or I/O memory space (depending on the 276 memory space timing to be configured). 277 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 278 279 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 280 (and data for write access) after the command de-assertion 281 for NAND-Flash read or write access to common/Attribute 282 or I/O memory space (depending on the memory space timing 283 to be configured). 284 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 285 286 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 287 data bus is kept in HiZ after the start of a NAND-Flash 288 write access to common/Attribute or I/O memory space (depending 289 on the memory space timing to be configured). 290 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 291 } FSMC_NAND_PCC_TimingTypeDef; 292 293 /** 294 * @brief FSMC PCCARD Configuration Structure definition 295 */ 296 typedef struct 297 { 298 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. 299 This parameter can be any value of @ref FSMC_Wait_feature */ 300 301 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 302 delay between CLE low and RE low. 303 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 304 305 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 306 delay between ALE low and RE low. 307 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 308 }FSMC_PCCARD_InitTypeDef; 309 310 /** 311 * @} 312 */ 313 314 /* Exported constants --------------------------------------------------------*/ 315 /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants 316 * @{ 317 */ 318 319 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller 320 * @{ 321 */ 322 323 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank 324 * @{ 325 */ 326 #define FSMC_NORSRAM_BANK1 (0x00000000U) 327 #define FSMC_NORSRAM_BANK2 (0x00000002U) 328 #define FSMC_NORSRAM_BANK3 (0x00000004U) 329 #define FSMC_NORSRAM_BANK4 (0x00000006U) 330 /** 331 * @} 332 */ 333 334 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing 335 * @{ 336 */ 337 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 338 #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 339 /** 340 * @} 341 */ 342 343 /** @defgroup FSMC_Memory_Type FSMC Memory Type 344 * @{ 345 */ 346 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) 347 #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) 348 #define FSMC_MEMORY_TYPE_NOR (0x00000008U) 349 /** 350 * @} 351 */ 352 353 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width 354 * @{ 355 */ 356 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 357 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 358 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 359 /** 360 * @} 361 */ 362 363 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access 364 * @{ 365 */ 366 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 367 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 368 /** 369 * @} 370 */ 371 372 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode 373 * @{ 374 */ 375 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 376 #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 377 /** 378 * @} 379 */ 380 381 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity 382 * @{ 383 */ 384 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 385 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 386 /** 387 * @} 388 */ 389 390 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 391 * @{ 392 */ 393 #define FSMC_WRAP_MODE_DISABLE (0x00000000U) 394 #define FSMC_WRAP_MODE_ENABLE (0x00000400U) 395 /** 396 * @} 397 */ 398 399 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing 400 * @{ 401 */ 402 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 403 #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) 404 /** 405 * @} 406 */ 407 408 /** @defgroup FSMC_Write_Operation FSMC Write Operation 409 * @{ 410 */ 411 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) 412 #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) 413 /** 414 * @} 415 */ 416 417 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal 418 * @{ 419 */ 420 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) 421 #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) 422 /** 423 * @} 424 */ 425 426 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode 427 * @{ 428 */ 429 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) 430 #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) 431 /** 432 * @} 433 */ 434 435 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait 436 * @{ 437 */ 438 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 439 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 440 /** 441 * @} 442 */ 443 444 /** @defgroup FSMC_Write_Burst FSMC Write Burst 445 * @{ 446 */ 447 #define FSMC_WRITE_BURST_DISABLE (0x00000000U) 448 #define FSMC_WRITE_BURST_ENABLE (0x00080000U) 449 /** 450 * @} 451 */ 452 453 /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock 454 * @{ 455 */ 456 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 457 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 458 /** 459 * @} 460 */ 461 462 /** @defgroup FSMC_Access_Mode FSMC Access Mode 463 * @{ 464 */ 465 #define FSMC_ACCESS_MODE_A (0x00000000U) 466 #define FSMC_ACCESS_MODE_B (0x10000000U) 467 #define FSMC_ACCESS_MODE_C (0x20000000U) 468 #define FSMC_ACCESS_MODE_D (0x30000000U) 469 /** 470 * @} 471 */ 472 473 /** 474 * @} 475 */ 476 477 478 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller 479 * @{ 480 */ 481 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank 482 * @{ 483 */ 484 #define FSMC_NAND_BANK2 (0x00000010U) 485 #define FSMC_NAND_BANK3 (0x00000100U) 486 /** 487 * @} 488 */ 489 490 /** @defgroup FSMC_Wait_feature FSMC Wait feature 491 * @{ 492 */ 493 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) 494 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) 495 /** 496 * @} 497 */ 498 499 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type 500 * @{ 501 */ 502 #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) 503 #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 504 /** 505 * @} 506 */ 507 508 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width 509 * @{ 510 */ 511 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) 512 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) 513 /** 514 * @} 515 */ 516 517 /** @defgroup FSMC_ECC FSMC ECC 518 * @{ 519 */ 520 #define FSMC_NAND_ECC_DISABLE (0x00000000U) 521 #define FSMC_NAND_ECC_ENABLE (0x00000040U) 522 /** 523 * @} 524 */ 525 526 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size 527 * @{ 528 */ 529 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 530 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 531 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 532 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 533 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 534 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 535 /** 536 * @} 537 */ 538 539 /** 540 * @} 541 */ 542 543 544 /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition 545 * @{ 546 */ 547 #define FSMC_IT_RISING_EDGE (0x00000008U) 548 #define FSMC_IT_LEVEL (0x00000010U) 549 #define FSMC_IT_FALLING_EDGE (0x00000020U) 550 /** 551 * @} 552 */ 553 554 /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition 555 * @{ 556 */ 557 #define FSMC_FLAG_RISING_EDGE (0x00000001U) 558 #define FSMC_FLAG_LEVEL (0x00000002U) 559 #define FSMC_FLAG_FALLING_EDGE (0x00000004U) 560 #define FSMC_FLAG_FEMPT (0x00000040U) 561 /** 562 * @} 563 */ 564 565 /** 566 * @} 567 */ 568 569 /** 570 * @} 571 */ 572 573 /* Private macro -------------------------------------------------------------*/ 574 /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros 575 * @{ 576 */ 577 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros 578 * @brief macros to handle NOR device enable/disable and read/write operations 579 * @{ 580 */ 581 582 /** 583 * @brief Enable the NORSRAM device access. 584 * @param __INSTANCE__ FSMC_NORSRAM Instance 585 * @param __BANK__ FSMC_NORSRAM Bank 586 * @retval None 587 */ 588 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 589 |= FSMC_BCR1_MBKEN) 590 591 /** 592 * @brief Disable the NORSRAM device access. 593 * @param __INSTANCE__ FSMC_NORSRAM Instance 594 * @param __BANK__ FSMC_NORSRAM Bank 595 * @retval None 596 */ 597 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 598 &= ~FSMC_BCR1_MBKEN) 599 600 /** 601 * @} 602 */ 603 604 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros 605 * @brief macros to handle NAND device enable/disable 606 * @{ 607 */ 608 609 /** 610 * @brief Enable the NAND device access. 611 * @param __INSTANCE__ FSMC_NAND Instance 612 * @param __BANK__ FSMC_NAND Bank 613 * @retval None 614 */ 615 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ 616 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) 617 618 /** 619 * @brief Disable the NAND device access. 620 * @param __INSTANCE__ FSMC_NAND Instance 621 * @param __BANK__ FSMC_NAND Bank 622 * @retval None 623 */ 624 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \ 625 CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) 626 627 /** 628 * @} 629 */ 630 631 /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros 632 * @brief macros to handle PCCARD read/write operations 633 * @{ 634 */ 635 /** 636 * @brief Enable the PCCARD device access. 637 * @param __INSTANCE__ FSMC_PCCARD Instance 638 * @retval None 639 */ 640 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) 641 642 /** 643 * @brief Disable the PCCARD device access. 644 * @param __INSTANCE__ FSMC_PCCARD Instance 645 * @retval None 646 */ 647 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) 648 /** 649 * @} 650 */ 651 652 /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt 653 * @brief macros to handle NAND interrupts 654 * @{ 655 */ 656 657 /** 658 * @brief Enable the NAND device interrupt. 659 * @param __INSTANCE__ FSMC_NAND instance 660 * @param __BANK__ FSMC_NAND Bank 661 * @param __INTERRUPT__ FSMC_NAND interrupt 662 * This parameter can be any combination of the following values: 663 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 664 * @arg FSMC_IT_LEVEL: Interrupt level. 665 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 666 * @retval None 667 */ 668 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ 669 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) 670 671 /** 672 * @brief Disable the NAND device interrupt. 673 * @param __INSTANCE__ FSMC_NAND Instance 674 * @param __BANK__ FSMC_NAND Bank 675 * @param __INTERRUPT__ FSMC_NAND interrupt 676 * This parameter can be any combination of the following values: 677 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 678 * @arg FSMC_IT_LEVEL: Interrupt level. 679 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 680 * @retval None 681 */ 682 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ 683 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 684 685 /** 686 * @brief Get flag status of the NAND device. 687 * @param __INSTANCE__ FSMC_NAND Instance 688 * @param __BANK__ FSMC_NAND Bank 689 * @param __FLAG__ FSMC_NAND flag 690 * This parameter can be any combination of the following values: 691 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 692 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 693 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 694 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 695 * @retval The state of FLAG (SET or RESET). 696 */ 697 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ 698 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) 699 700 /** 701 * @brief Clear flag status of the NAND device. 702 * @param __INSTANCE__ FSMC_NAND Instance 703 * @param __BANK__ FSMC_NAND Bank 704 * @param __FLAG__ FSMC_NAND flag 705 * This parameter can be any combination of the following values: 706 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 707 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 708 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 709 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 710 * @retval None 711 */ 712 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ 713 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 714 715 /** 716 * @} 717 */ 718 719 /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt 720 * @brief macros to handle PCCARD interrupts 721 * @{ 722 */ 723 724 /** 725 * @brief Enable the PCCARD device interrupt. 726 * @param __INSTANCE__ FSMC_PCCARD instance 727 * @param __INTERRUPT__ FSMC_PCCARD interrupt 728 * This parameter can be any combination of the following values: 729 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 730 * @arg FSMC_IT_LEVEL: Interrupt level. 731 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 732 * @retval None 733 */ 734 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) 735 736 /** 737 * @brief Disable the PCCARD device interrupt. 738 * @param __INSTANCE__ FSMC_PCCARD instance 739 * @param __INTERRUPT__ FSMC_PCCARD interrupt 740 * This parameter can be any combination of the following values: 741 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 742 * @arg FSMC_IT_LEVEL: Interrupt level. 743 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 744 * @retval None 745 */ 746 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 747 748 /** 749 * @brief Get flag status of the PCCARD device. 750 * @param __INSTANCE__ FSMC_PCCARD instance 751 * @param __FLAG__ FSMC_PCCARD flag 752 * This parameter can be any combination of the following values: 753 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 754 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 755 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 756 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 757 * @retval The state of FLAG (SET or RESET). 758 */ 759 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) 760 761 /** 762 * @brief Clear flag status of the PCCARD device. 763 * @param __INSTANCE__ FSMC_PCCARD instance 764 * @param __FLAG__ FSMC_PCCARD flag 765 * This parameter can be any combination of the following values: 766 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 767 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 768 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 769 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 770 * @retval None 771 */ 772 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) 773 774 /** 775 * @} 776 */ 777 778 /** 779 * @} 780 */ 781 782 /** 783 * @} 784 */ 785 786 /* Private functions ---------------------------------------------------------*/ 787 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions 788 * @{ 789 */ 790 791 /** @defgroup FSMC_LL_NORSRAM NOR SRAM 792 * @{ 793 */ 794 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 795 * @{ 796 */ 797 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, 798 FSMC_NORSRAM_InitTypeDef *Init); 799 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, 800 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 801 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, 802 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 803 uint32_t ExtendedMode); 804 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, 805 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 806 /** 807 * @} 808 */ 809 810 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 811 * @{ 812 */ 813 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 814 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 815 /** 816 * @} 817 */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup FSMC_LL_NAND NAND 823 * @{ 824 */ 825 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 826 * @{ 827 */ 828 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); 829 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 830 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 831 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 832 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 833 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); 834 /** 835 * @} 836 */ 837 838 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions 839 * @{ 840 */ 841 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 842 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 843 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 844 uint32_t Timeout); 845 /** 846 * @} 847 */ 848 /** 849 * @} 850 */ 851 852 /** @defgroup FSMC_LL_PCCARD PCCARD 853 * @{ 854 */ 855 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 856 * @{ 857 */ 858 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); 859 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 860 FSMC_NAND_PCC_TimingTypeDef *Timing); 861 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 862 FSMC_NAND_PCC_TimingTypeDef *Timing); 863 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 864 FSMC_NAND_PCC_TimingTypeDef *Timing); 865 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); 866 /** 867 * @} 868 */ 869 /** 870 * @} 871 */ 872 873 874 /** 875 * @} 876 */ 877 878 /** 879 * @} 880 */ 881 882 /** 883 * @} 884 */ 885 886 #ifdef __cplusplus 887 } 888 #endif 889 890 #endif /* STM32F2xx_LL_FSMC_H */ 891
