Lines Matching refs:Device
189 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
197 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
215 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
273 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
286 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
290 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
295 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
301 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
306 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
309 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
323 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Timing_Init() argument
329 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Timing_Init()
340 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
349 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
351 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
353 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
371 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, in FMC_NORSRAM_Extended_Timing_Init() argument
382 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); in FMC_NORSRAM_Extended_Timing_Init()
391 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
399 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
429 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Enable() argument
432 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Enable()
436 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
447 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Disable() argument
450 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Disable()
454 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Disable()
517 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
520 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_Init()
530 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
549 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_CommonSpace_Timing_Init() argument
553 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_CommonSpace_Timing_Init()
564 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
580 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_AttributeSpace_Timing_Init() argument
584 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_AttributeSpace_Timing_Init()
595 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
609 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_DeInit() argument
612 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_DeInit()
616 __FMC_NAND_DISABLE(Device, Bank); in FMC_NAND_DeInit()
623 WRITE_REG(Device->PCR, 0x00000018U); in FMC_NAND_DeInit()
624 WRITE_REG(Device->SR, 0x00000040U); in FMC_NAND_DeInit()
625 WRITE_REG(Device->PMEM, 0xFCFCFCFCU); in FMC_NAND_DeInit()
626 WRITE_REG(Device->PATT, 0xFCFCFCFCU); in FMC_NAND_DeInit()
657 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Enable() argument
660 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Enable()
667 SET_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Enable()
679 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Disable() argument
682 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Disable()
689 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Disable()
702 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, in FMC_NAND_GetECC() argument
708 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_GetECC()
715 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) in FMC_NAND_GetECC()
731 *ECCval = (uint32_t)Device->ECCR; in FMC_NAND_GetECC()
788 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
791 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Init()
806 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
820 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
828 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
850 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_Timing_Init() argument
854 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Timing_Init()
867 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
879 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
885 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
902 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_DeInit() argument
905 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_DeInit()
909 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
910 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
911 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
912 Device->SDRTR = 0x00000000U; in FMC_SDRAM_DeInit()
913 Device->SDSR = 0x00000000U; in FMC_SDRAM_DeInit()
943 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Enable() argument
946 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Enable()
950 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
960 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Disable() argument
963 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Disable()
967 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
980 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SendCommand() argument
984 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SendCommand()
991 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1006 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) in FMC_SDRAM_ProgramRefreshRate() argument
1009 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_ProgramRefreshRate()
1013 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); in FMC_SDRAM_ProgramRefreshRate()
1024 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SetAutoRefreshNumber() argument
1028 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SetAutoRefreshNumber()
1032 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
1046 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_GetModeStatus() argument
1051 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_GetModeStatus()
1057 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); in FMC_SDRAM_GetModeStatus()
1061 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); in FMC_SDRAM_GetModeStatus()