1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_LL_FMC_H 21 #define STM32H5xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK4)) 46 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 51 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 54 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 55 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 59 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 60 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 61 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 62 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 63 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 64 ((__MODE__) == FMC_ACCESS_MODE_D)) 65 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 66 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 67 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 68 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 69 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 70 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 71 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 72 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 73 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 74 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 75 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 76 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 77 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 78 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 79 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 80 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 81 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 82 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 83 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 84 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 85 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 86 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 87 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 88 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 89 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 90 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 91 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 92 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 93 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 94 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 95 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 96 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 97 98 99 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 100 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 101 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 102 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 103 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 104 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 105 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 106 107 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 108 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 109 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 110 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 113 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 114 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 115 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 116 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 117 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 118 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 120 121 122 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ 123 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16)) 124 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ 125 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 126 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ 127 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ 128 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 129 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ 130 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 131 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ 132 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ 133 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 134 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ 135 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ 136 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ 137 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ 138 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ 139 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ 140 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 141 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ 142 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ 143 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 144 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 145 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 146 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 147 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 148 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 149 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 150 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 151 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) 152 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) 153 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) 154 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 155 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ 156 ((__BANK__) == FMC_SDRAM_BANK2)) 157 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ 158 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ 159 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ 160 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 161 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ 162 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ 163 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) 164 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ 165 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 166 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ 167 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ 168 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) 169 170 171 /** 172 * @} 173 */ 174 175 /* Exported typedef ----------------------------------------------------------*/ 176 177 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 178 * @{ 179 */ 180 181 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 182 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 183 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 184 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 185 186 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 187 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 188 #define FMC_NAND_DEVICE FMC_Bank3_R 189 #define FMC_SDRAM_DEVICE FMC_Bank5_6_R 190 191 /** 192 * @brief FMC NORSRAM Configuration Structure definition 193 */ 194 typedef struct 195 { 196 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 197 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 198 199 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 200 multiplexed on the data bus or not. 201 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 202 203 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 204 the corresponding memory device. 205 This parameter can be a value of @ref FMC_Memory_Type */ 206 207 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 208 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 209 210 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 211 valid only with synchronous burst Flash memories. 212 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 213 214 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 215 the Flash memory in burst mode. 216 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 217 218 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 219 clock cycle before the wait state or during the wait state, 220 valid only when accessing memories in burst mode. 221 This parameter can be a value of @ref FMC_Wait_Timing */ 222 223 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 224 This parameter can be a value of @ref FMC_Write_Operation */ 225 226 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 227 signal, valid for Flash memory access in burst mode. 228 This parameter can be a value of @ref FMC_Wait_Signal */ 229 230 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 231 This parameter can be a value of @ref FMC_Extended_Mode */ 232 233 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 234 valid only with asynchronous Flash memories. 235 This parameter can be a value of @ref FMC_AsynchronousWait */ 236 237 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 238 This parameter can be a value of @ref FMC_Write_Burst */ 239 240 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 241 This parameter is only enabled through the FMC_BCR1 register, 242 and don't care through FMC_BCR2..4 registers. 243 This parameter can be a value of @ref FMC_Continous_Clock */ 244 245 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 246 This parameter is only enabled through the FMC_BCR1 register, 247 and don't care through FMC_BCR2..4 registers. 248 This parameter can be a value of @ref FMC_Write_FIFO */ 249 250 uint32_t PageSize; /*!< Specifies the memory page size. 251 This parameter can be a value of @ref FMC_Page_Size */ 252 253 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 254 This parameter can be a value of @ref FMC_Byte_Lane */ 255 256 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 257 NSBank for PSRAM refresh. 258 This parameter can be set to ENABLE or DISABLE */ 259 260 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 261 synchronous accesses and in HCLK cycles for asynchronous accesses, 262 valid only if MaxChipSelectPulse is ENABLE. 263 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 264 @note: This parameter is common to all NSBank. */ 265 } FMC_NORSRAM_InitTypeDef; 266 267 /** 268 * @brief FMC NORSRAM Timing parameters structure definition 269 */ 270 typedef struct 271 { 272 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 273 the duration of the address setup time. 274 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 275 @note This parameter is not used with synchronous NOR Flash memories. */ 276 277 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 278 the duration of the address hold time. 279 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 280 @note This parameter is not used with synchronous NOR Flash memories. */ 281 282 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 283 the duration of the data setup time. 284 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 285 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 286 NOR Flash memories. */ 287 288 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 289 the duration of the data hold time. 290 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 291 @note This parameter is used for used in asynchronous accesses. */ 292 293 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 294 the duration of the bus turnaround. 295 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 296 @note This parameter is only used for multiplexed NOR Flash memories. */ 297 298 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 299 HCLK cycles. This parameter can be a value between Min_Data = 2 and 300 Max_Data = 16. 301 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 302 accesses. */ 303 304 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 305 to the memory before getting the first data. 306 The parameter value depends on the memory type as shown below: 307 - It must be set to 0 in case of a CRAM 308 - It is don't care in asynchronous NOR, SRAM or ROM accesses 309 - It may assume a value between Min_Data = 2 and Max_Data = 17 310 in NOR Flash memories with synchronous burst mode enable */ 311 312 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 313 This parameter can be a value of @ref FMC_Access_Mode */ 314 } FMC_NORSRAM_TimingTypeDef; 315 316 /** 317 * @brief FMC NAND Configuration Structure definition 318 */ 319 typedef struct 320 { 321 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 322 This parameter can be a value of @ref FMC_NAND_Bank */ 323 324 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 325 This parameter can be any value of @ref FMC_Wait_feature */ 326 327 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 328 This parameter can be any value of @ref FMC_NAND_Data_Width */ 329 330 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 331 This parameter can be any value of @ref FMC_ECC */ 332 333 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 334 This parameter can be any value of @ref FMC_ECC_Page_Size */ 335 336 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 337 delay between CLE low and RE low. 338 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 339 340 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 341 delay between ALE low and RE low. 342 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 343 } FMC_NAND_InitTypeDef; 344 345 /** 346 * @brief FMC NAND Timing parameters structure definition 347 */ 348 typedef struct 349 { 350 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 351 the command assertion for NAND-Flash read or write access 352 to common/Attribute or I/O memory space (depending on 353 the memory space timing to be configured). 354 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 355 356 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 357 command for NAND-Flash read or write access to 358 common/Attribute or I/O memory space (depending on the 359 memory space timing to be configured). 360 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 361 362 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 363 (and data for write access) after the command de-assertion 364 for NAND-Flash read or write access to common/Attribute 365 or I/O memory space (depending on the memory space timing 366 to be configured). 367 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 368 369 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 370 data bus is kept in HiZ after the start of a NAND-Flash 371 write access to common/Attribute or I/O memory space (depending 372 on the memory space timing to be configured). 373 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 374 } FMC_NAND_PCC_TimingTypeDef; 375 376 377 /** 378 * @brief FMC SDRAM Configuration Structure definition 379 */ 380 typedef struct 381 { 382 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. 383 This parameter can be a value of @ref FMC_SDRAM_Bank */ 384 385 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. 386 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ 387 388 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. 389 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ 390 391 uint32_t MemoryDataWidth; /*!< Defines the memory device width. 392 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ 393 394 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. 395 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ 396 397 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. 398 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ 399 400 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. 401 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ 402 403 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 404 to disable the clock before changing frequency. 405 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ 406 407 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read 408 commands during the CAS latency and stores data in the Read FIFO. 409 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ 410 411 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. 412 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ 413 } FMC_SDRAM_InitTypeDef; 414 415 /** 416 * @brief FMC SDRAM Timing parameters structure definition 417 */ 418 typedef struct 419 { 420 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and 421 an active or Refresh command in number of memory clock cycles. 422 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 423 424 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to 425 issuing the Activate command in number of memory clock cycles. 426 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 427 428 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock 429 cycles. 430 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 431 432 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command 433 and the delay between two consecutive Refresh commands in number of 434 memory clock cycles. 435 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 436 437 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. 438 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 439 440 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command 441 in number of memory clock cycles. 442 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 443 444 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write 445 command in number of memory clock cycles. 446 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 447 } FMC_SDRAM_TimingTypeDef; 448 449 /** 450 * @brief SDRAM command parameters structure definition 451 */ 452 typedef struct 453 { 454 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. 455 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ 456 457 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. 458 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ 459 460 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued 461 in auto refresh mode. 462 This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ 463 464 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ 465 } FMC_SDRAM_CommandTypeDef; 466 /** 467 * @} 468 */ 469 470 /* Exported constants --------------------------------------------------------*/ 471 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 472 * @{ 473 */ 474 475 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 476 * @{ 477 */ 478 479 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 480 * @{ 481 */ 482 #define FMC_NORSRAM_BANK1 (0x00000000U) 483 #define FMC_NORSRAM_BANK2 (0x00000002U) 484 #define FMC_NORSRAM_BANK3 (0x00000004U) 485 #define FMC_NORSRAM_BANK4 (0x00000006U) 486 /** 487 * @} 488 */ 489 490 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 491 * @{ 492 */ 493 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 494 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 495 /** 496 * @} 497 */ 498 499 /** @defgroup FMC_Memory_Type FMC Memory Type 500 * @{ 501 */ 502 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 503 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 504 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 505 /** 506 * @} 507 */ 508 509 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 510 * @{ 511 */ 512 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 513 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 514 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 515 /** 516 * @} 517 */ 518 519 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 520 * @{ 521 */ 522 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 523 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 524 /** 525 * @} 526 */ 527 528 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 529 * @{ 530 */ 531 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 532 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 533 /** 534 * @} 535 */ 536 537 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 538 * @{ 539 */ 540 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 541 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 542 /** 543 * @} 544 */ 545 546 /** @defgroup FMC_Wait_Timing FMC Wait Timing 547 * @{ 548 */ 549 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 550 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 551 /** 552 * @} 553 */ 554 555 /** @defgroup FMC_Write_Operation FMC Write Operation 556 * @{ 557 */ 558 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 559 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 560 /** 561 * @} 562 */ 563 564 /** @defgroup FMC_Wait_Signal FMC Wait Signal 565 * @{ 566 */ 567 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 568 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 569 /** 570 * @} 571 */ 572 573 /** @defgroup FMC_Extended_Mode FMC Extended Mode 574 * @{ 575 */ 576 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 577 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 578 /** 579 * @} 580 */ 581 582 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 583 * @{ 584 */ 585 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 586 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 587 /** 588 * @} 589 */ 590 591 /** @defgroup FMC_Page_Size FMC Page Size 592 * @{ 593 */ 594 #define FMC_PAGE_SIZE_NONE (0x00000000U) 595 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 596 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 597 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 598 | FMC_BCRx_CPSIZE_1) 599 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 600 /** 601 * @} 602 */ 603 604 /** @defgroup FMC_Write_Burst FMC Write Burst 605 * @{ 606 */ 607 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 608 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 609 /** 610 * @} 611 */ 612 613 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 614 * @{ 615 */ 616 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 617 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 618 /** 619 * @} 620 */ 621 622 #if defined(FMC_BCR1_WFDIS) 623 /** @defgroup FMC_Write_FIFO FMC Write FIFO 624 * @{ 625 */ 626 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 627 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 628 #endif /* FMC_BCR1_WFDIS */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup FMC_Access_Mode FMC Access Mode 634 * @{ 635 */ 636 #define FMC_ACCESS_MODE_A (0x00000000U) 637 #define FMC_ACCESS_MODE_B (0x10000000U) 638 #define FMC_ACCESS_MODE_C (0x20000000U) 639 #define FMC_ACCESS_MODE_D (0x30000000U) 640 /** 641 * @} 642 */ 643 644 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 645 * @{ 646 */ 647 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 648 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 649 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 650 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 651 /** 652 * @} 653 */ 654 655 /** 656 * @} 657 */ 658 659 660 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 661 * @{ 662 */ 663 /** @defgroup FMC_NAND_Bank FMC NAND Bank 664 * @{ 665 */ 666 #define FMC_NAND_BANK3 (0x00000100U) 667 /** 668 * @} 669 */ 670 671 /** @defgroup FMC_Wait_feature FMC Wait feature 672 * @{ 673 */ 674 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 675 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 676 /** 677 * @} 678 */ 679 680 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 681 * @{ 682 */ 683 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 684 /** 685 * @} 686 */ 687 688 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 689 * @{ 690 */ 691 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 692 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 693 /** 694 * @} 695 */ 696 697 /** @defgroup FMC_ECC FMC ECC 698 * @{ 699 */ 700 #define FMC_NAND_ECC_DISABLE (0x00000000U) 701 #define FMC_NAND_ECC_ENABLE (0x00000040U) 702 /** 703 * @} 704 */ 705 706 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 707 * @{ 708 */ 709 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 710 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 711 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 712 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 713 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 714 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 715 /** 716 * @} 717 */ 718 719 /** 720 * @} 721 */ 722 723 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 724 * @{ 725 */ 726 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank 727 * @{ 728 */ 729 #define FMC_SDRAM_BANK1 (0x00000000U) 730 #define FMC_SDRAM_BANK2 (0x00000001U) 731 /** 732 * @} 733 */ 734 735 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 736 * @{ 737 */ 738 #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) 739 #define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) 740 #define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) 741 #define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) 742 /** 743 * @} 744 */ 745 746 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number 747 * @{ 748 */ 749 #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) 750 #define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) 751 #define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) 752 /** 753 * @} 754 */ 755 756 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width 757 * @{ 758 */ 759 #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) 760 #define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) 761 /** 762 * @} 763 */ 764 765 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number 766 * @{ 767 */ 768 #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) 769 #define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) 770 /** 771 * @} 772 */ 773 774 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency 775 * @{ 776 */ 777 #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) 778 #define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) 779 #define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) 780 /** 781 * @} 782 */ 783 784 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection 785 * @{ 786 */ 787 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) 788 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) 789 /** 790 * @} 791 */ 792 793 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period 794 * @{ 795 */ 796 #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) 797 #define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) 798 #define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) 799 /** 800 * @} 801 */ 802 803 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst 804 * @{ 805 */ 806 #define FMC_SDRAM_RBURST_DISABLE (0x00000000U) 807 #define FMC_SDRAM_RBURST_ENABLE (0x00001000U) 808 /** 809 * @} 810 */ 811 812 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay 813 * @{ 814 */ 815 #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) 816 #define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) 817 #define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) 818 /** 819 * @} 820 */ 821 822 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode 823 * @{ 824 */ 825 #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) 826 #define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) 827 #define FMC_SDRAM_CMD_PALL (0x00000002U) 828 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) 829 #define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) 830 #define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) 831 #define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) 832 /** 833 * @} 834 */ 835 836 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target 837 * @{ 838 */ 839 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 840 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 841 #define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) 842 /** 843 * @} 844 */ 845 846 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 847 * @{ 848 */ 849 #define FMC_SDRAM_NORMAL_MODE (0x00000000U) 850 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 851 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 852 /** 853 * @} 854 */ 855 856 /** 857 * @} 858 */ 859 860 861 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 862 * @{ 863 */ 864 #define FMC_IT_RISING_EDGE (0x00000008U) 865 #define FMC_IT_LEVEL (0x00000010U) 866 #define FMC_IT_FALLING_EDGE (0x00000020U) 867 #define FMC_IT_REFRESH_ERROR (0x00004000U) 868 /** 869 * @} 870 */ 871 872 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 873 * @{ 874 */ 875 #define FMC_FLAG_RISING_EDGE (0x00000001U) 876 #define FMC_FLAG_LEVEL (0x00000002U) 877 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 878 #define FMC_FLAG_FEMPT (0x00000040U) 879 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 880 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 881 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 882 /** 883 * @} 884 */ 885 886 /** 887 * @} 888 */ 889 890 /** 891 * @} 892 */ 893 894 /* Private macro -------------------------------------------------------------*/ 895 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 896 * @{ 897 */ 898 /** 899 * @brief Enable the FMC Peripheral. 900 * @retval None 901 */ 902 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) 903 904 /** 905 * @brief Disable the FMC Peripheral. 906 * @retval None 907 */ 908 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) 909 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 910 * @brief macros to handle NOR device enable/disable and read/write operations 911 * @{ 912 */ 913 914 /** 915 * @brief Enable the NORSRAM device access. 916 * @param __INSTANCE__ FMC_NORSRAM Instance 917 * @param __BANK__ FMC_NORSRAM Bank 918 * @retval None 919 */ 920 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 921 |= FMC_BCRx_MBKEN) 922 923 /** 924 * @brief Disable the NORSRAM device access. 925 * @param __INSTANCE__ FMC_NORSRAM Instance 926 * @param __BANK__ FMC_NORSRAM Bank 927 * @retval None 928 */ 929 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 930 &= ~FMC_BCRx_MBKEN) 931 932 /** 933 * @} 934 */ 935 936 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 937 * @brief macros to handle NAND device enable/disable 938 * @{ 939 */ 940 941 /** 942 * @brief Enable the NAND device access. 943 * @param __INSTANCE__ FMC_NAND Instance 944 * @retval None 945 */ 946 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 947 948 /** 949 * @brief Disable the NAND device access. 950 * @param __INSTANCE__ FMC_NAND Instance 951 * @param __BANK__ FMC_NAND Bank 952 * @retval None 953 */ 954 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 955 956 /** 957 * @} 958 */ 959 960 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 961 * @brief macros to handle NAND interrupts 962 * @{ 963 */ 964 965 /** 966 * @brief Enable the NAND device interrupt. 967 * @param __INSTANCE__ FMC_NAND instance 968 * @param __INTERRUPT__ FMC_NAND interrupt 969 * This parameter can be any combination of the following values: 970 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 971 * @arg FMC_IT_LEVEL: Interrupt level. 972 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 973 * @retval None 974 */ 975 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 976 977 /** 978 * @brief Disable the NAND device interrupt. 979 * @param __INSTANCE__ FMC_NAND Instance 980 * @param __INTERRUPT__ FMC_NAND interrupt 981 * This parameter can be any combination of the following values: 982 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 983 * @arg FMC_IT_LEVEL: Interrupt level. 984 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 985 * @retval None 986 */ 987 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 988 989 /** 990 * @brief Get flag status of the NAND device. 991 * @param __INSTANCE__ FMC_NAND Instance 992 * @param __BANK__ FMC_NAND Bank 993 * @param __FLAG__ FMC_NAND flag 994 * This parameter can be any combination of the following values: 995 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 996 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 997 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 998 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 999 * @retval The state of FLAG (SET or RESET). 1000 */ 1001 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 1002 1003 /** 1004 * @brief Clear flag status of the NAND device. 1005 * @param __INSTANCE__ FMC_NAND Instance 1006 * @param __FLAG__ FMC_NAND flag 1007 * This parameter can be any combination of the following values: 1008 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1009 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1010 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1011 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1012 * @retval None 1013 */ 1014 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 1015 1016 /** 1017 * @} 1018 */ 1019 1020 1021 /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt 1022 * @brief macros to handle SDRAM interrupts 1023 * @{ 1024 */ 1025 1026 /** 1027 * @brief Enable the SDRAM device interrupt. 1028 * @param __INSTANCE__ FMC_SDRAM instance 1029 * @param __INTERRUPT__ FMC_SDRAM interrupt 1030 * This parameter can be any combination of the following values: 1031 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1032 * @retval None 1033 */ 1034 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 1035 1036 /** 1037 * @brief Disable the SDRAM device interrupt. 1038 * @param __INSTANCE__ FMC_SDRAM instance 1039 * @param __INTERRUPT__ FMC_SDRAM interrupt 1040 * This parameter can be any combination of the following values: 1041 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1042 * @retval None 1043 */ 1044 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 1045 1046 /** 1047 * @brief Get flag status of the SDRAM device. 1048 * @param __INSTANCE__ FMC_SDRAM instance 1049 * @param __FLAG__ FMC_SDRAM flag 1050 * This parameter can be any combination of the following values: 1051 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. 1052 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. 1053 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. 1054 * @retval The state of FLAG (SET or RESET). 1055 */ 1056 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 1057 1058 /** 1059 * @brief Clear flag status of the SDRAM device. 1060 * @param __INSTANCE__ FMC_SDRAM instance 1061 * @param __FLAG__ FMC_SDRAM flag 1062 * This parameter can be any combination of the following values: 1063 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR 1064 * @retval None 1065 */ 1066 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 1067 1068 /** 1069 * @} 1070 */ 1071 /** 1072 * @} 1073 */ 1074 1075 /** 1076 * @} 1077 */ 1078 1079 /* Private functions ---------------------------------------------------------*/ 1080 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 1081 * @{ 1082 */ 1083 1084 /** @defgroup FMC_LL_NORSRAM NOR SRAM 1085 * @{ 1086 */ 1087 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 1088 * @{ 1089 */ 1090 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 1091 FMC_NORSRAM_InitTypeDef *Init); 1092 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 1093 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 1094 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 1095 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 1096 uint32_t ExtendedMode); 1097 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 1098 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 1099 /** 1100 * @} 1101 */ 1102 1103 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1104 * @{ 1105 */ 1106 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1107 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1108 /** 1109 * @} 1110 */ 1111 /** 1112 * @} 1113 */ 1114 1115 /** @defgroup FMC_LL_NAND NAND 1116 * @{ 1117 */ 1118 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1119 * @{ 1120 */ 1121 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 1122 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1123 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1124 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1125 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1126 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 1127 /** 1128 * @} 1129 */ 1130 1131 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1132 * @{ 1133 */ 1134 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1135 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1136 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 1137 uint32_t Timeout); 1138 /** 1139 * @} 1140 */ 1141 /** 1142 * @} 1143 */ 1144 1145 1146 /** @defgroup FMC_LL_SDRAM SDRAM 1147 * @{ 1148 */ 1149 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 1150 * @{ 1151 */ 1152 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); 1153 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, 1154 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); 1155 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1156 /** 1157 * @} 1158 */ 1159 1160 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 1161 * @{ 1162 */ 1163 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1164 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1165 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, 1166 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); 1167 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); 1168 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, 1169 uint32_t AutoRefreshNumber); 1170 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1171 /** 1172 * @} 1173 */ 1174 /** 1175 * @} 1176 */ 1177 1178 /** 1179 * @} 1180 */ 1181 1182 /** 1183 * @} 1184 */ 1185 1186 /** 1187 * @} 1188 */ 1189 1190 #ifdef __cplusplus 1191 } 1192 #endif 1193 1194 #endif /* STM32H5xx_LL_FMC_H */ 1195
