1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_LL_FMC_H 21 #define STM32L4xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_BANK1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 60 #if defined(FMC_BCR1_WFDIS) 61 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 62 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 63 #endif /* FMC_BCR1_WFDIS */ 64 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 65 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 66 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 67 ((__MODE__) == FMC_ACCESS_MODE_D)) 68 #if defined(FMC_BCRx_NBLSET) 69 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 70 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 71 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 72 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 73 #endif /* FMC_BCRx_NBLSET */ 74 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 75 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 76 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 77 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 78 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 79 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 80 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 81 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 82 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 83 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 84 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 85 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 86 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 87 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 88 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 89 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 90 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 91 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 92 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 93 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 95 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 96 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 97 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 98 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 99 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 100 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 101 #if defined(FMC_PCSCNTR_CSCOUNT) 102 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 103 #endif /* FMC_PCSCNTR_CSCOUNT */ 104 105 #endif /* FMC_BANK1 */ 106 #if defined(FMC_BANK3) 107 108 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 109 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 110 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 111 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 112 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 113 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 114 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 115 116 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 117 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 118 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 119 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 120 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 121 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 122 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 123 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 124 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 125 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 126 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 127 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 128 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 129 130 #endif /* FMC_BANK3 */ 131 132 /** 133 * @} 134 */ 135 136 /* Exported typedef ----------------------------------------------------------*/ 137 138 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 139 * @{ 140 */ 141 142 #if defined(FMC_BANK1) 143 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 144 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 145 #endif /* FMC_BANK1 */ 146 #if defined(FMC_BANK3) 147 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 148 #endif /* FMC_BANK3 */ 149 150 #if defined(FMC_BANK1) 151 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 152 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 153 #endif /* FMC_BANK1 */ 154 #if defined(FMC_BANK3) 155 #define FMC_NAND_DEVICE FMC_Bank3_R 156 #endif /* FMC_BANK3 */ 157 158 #if defined(FMC_BANK1) 159 /** 160 * @brief FMC NORSRAM Configuration Structure definition 161 */ 162 typedef struct 163 { 164 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 165 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 166 167 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 168 multiplexed on the data bus or not. 169 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 170 171 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 172 the corresponding memory device. 173 This parameter can be a value of @ref FMC_Memory_Type */ 174 175 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 176 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 177 178 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 179 valid only with synchronous burst Flash memories. 180 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 181 182 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 183 the Flash memory in burst mode. 184 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 185 186 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 187 clock cycle before the wait state or during the wait state, 188 valid only when accessing memories in burst mode. 189 This parameter can be a value of @ref FMC_Wait_Timing */ 190 191 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 192 This parameter can be a value of @ref FMC_Write_Operation */ 193 194 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 195 signal, valid for Flash memory access in burst mode. 196 This parameter can be a value of @ref FMC_Wait_Signal */ 197 198 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 199 This parameter can be a value of @ref FMC_Extended_Mode */ 200 201 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 202 valid only with asynchronous Flash memories. 203 This parameter can be a value of @ref FMC_AsynchronousWait */ 204 205 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 206 This parameter can be a value of @ref FMC_Write_Burst */ 207 208 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 209 This parameter is only enabled through the FMC_BCR1 register, 210 and don't care through FMC_BCR2..4 registers. 211 This parameter can be a value of @ref FMC_Continous_Clock */ 212 213 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 214 This parameter is only enabled through the FMC_BCR1 register, 215 and don't care through FMC_BCR2..4 registers. 216 This parameter can be a value of @ref FMC_Write_FIFO */ 217 218 uint32_t PageSize; /*!< Specifies the memory page size. 219 This parameter can be a value of @ref FMC_Page_Size */ 220 221 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 222 This parameter can be a value of @ref FMC_Byte_Lane */ 223 #if defined(FMC_PCSCNTR_CSCOUNT) 224 225 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 226 NSBank for PSRAM refresh. 227 This parameter can be set to ENABLE or DISABLE */ 228 229 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 230 synchronous accesses and in HCLK cycles for asynchronous accesses, 231 valid only if MaxChipSelectPulse is ENABLE. 232 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 233 @note: This parameter is common to all NSBank. */ 234 #endif 235 } FMC_NORSRAM_InitTypeDef; 236 237 /** 238 * @brief FMC NORSRAM Timing parameters structure definition 239 */ 240 typedef struct 241 { 242 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 243 the duration of the address setup time. 244 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 245 @note This parameter is not used with synchronous NOR Flash memories. */ 246 247 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 248 the duration of the address hold time. 249 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 250 @note This parameter is not used with synchronous NOR Flash memories. */ 251 252 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 253 the duration of the data setup time. 254 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 255 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 256 NOR Flash memories. */ 257 258 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 259 the duration of the data hold time. 260 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 261 @note This parameter is used for used in asynchronous accesses. */ 262 263 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 264 the duration of the bus turnaround. 265 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 266 @note This parameter is only used for multiplexed NOR Flash memories. */ 267 268 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 269 HCLK cycles. This parameter can be a value between Min_Data = 2 and 270 Max_Data = 16. 271 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 272 accesses. */ 273 274 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 275 to the memory before getting the first data. 276 The parameter value depends on the memory type as shown below: 277 - It must be set to 0 in case of a CRAM 278 - It is don't care in asynchronous NOR, SRAM or ROM accesses 279 - It may assume a value between Min_Data = 2 and Max_Data = 17 280 in NOR Flash memories with synchronous burst mode enable */ 281 282 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 283 This parameter can be a value of @ref FMC_Access_Mode */ 284 } FMC_NORSRAM_TimingTypeDef; 285 #endif /* FMC_BANK1 */ 286 287 #if defined(FMC_BANK3) 288 /** 289 * @brief FMC NAND Configuration Structure definition 290 */ 291 typedef struct 292 { 293 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 294 This parameter can be a value of @ref FMC_NAND_Bank */ 295 296 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 297 This parameter can be any value of @ref FMC_Wait_feature */ 298 299 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 300 This parameter can be any value of @ref FMC_NAND_Data_Width */ 301 302 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 303 This parameter can be any value of @ref FMC_ECC */ 304 305 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 306 This parameter can be any value of @ref FMC_ECC_Page_Size */ 307 308 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 309 delay between CLE low and RE low. 310 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 311 312 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 313 delay between ALE low and RE low. 314 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 315 } FMC_NAND_InitTypeDef; 316 #endif 317 318 #if defined(FMC_BANK3) 319 /** 320 * @brief FMC NAND Timing parameters structure definition 321 */ 322 typedef struct 323 { 324 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 325 the command assertion for NAND-Flash read or write access 326 to common/Attribute or I/O memory space (depending on 327 the memory space timing to be configured). 328 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 329 330 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 331 command for NAND-Flash read or write access to 332 common/Attribute or I/O memory space (depending on the 333 memory space timing to be configured). 334 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 335 336 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 337 (and data for write access) after the command de-assertion 338 for NAND-Flash read or write access to common/Attribute 339 or I/O memory space (depending on the memory space timing 340 to be configured). 341 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 342 343 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 344 data bus is kept in HiZ after the start of a NAND-Flash 345 write access to common/Attribute or I/O memory space (depending 346 on the memory space timing to be configured). 347 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 348 } FMC_NAND_PCC_TimingTypeDef; 349 #endif /* FMC_BANK3 */ 350 351 352 /** 353 * @} 354 */ 355 356 /* Exported constants --------------------------------------------------------*/ 357 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 358 * @{ 359 */ 360 #if defined(FMC_BANK1) 361 362 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 363 * @{ 364 */ 365 366 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 367 * @{ 368 */ 369 #define FMC_NORSRAM_BANK1 (0x00000000U) 370 #define FMC_NORSRAM_BANK2 (0x00000002U) 371 #define FMC_NORSRAM_BANK3 (0x00000004U) 372 #define FMC_NORSRAM_BANK4 (0x00000006U) 373 /** 374 * @} 375 */ 376 377 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 378 * @{ 379 */ 380 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 381 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 382 /** 383 * @} 384 */ 385 386 /** @defgroup FMC_Memory_Type FMC Memory Type 387 * @{ 388 */ 389 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 390 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 391 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 392 /** 393 * @} 394 */ 395 396 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 397 * @{ 398 */ 399 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 400 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 401 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 402 /** 403 * @} 404 */ 405 406 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 407 * @{ 408 */ 409 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 410 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 411 /** 412 * @} 413 */ 414 415 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 416 * @{ 417 */ 418 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 419 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 420 /** 421 * @} 422 */ 423 424 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 425 * @{ 426 */ 427 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 428 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 429 /** 430 * @} 431 */ 432 433 /** @defgroup FMC_Wait_Timing FMC Wait Timing 434 * @{ 435 */ 436 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 437 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 438 /** 439 * @} 440 */ 441 442 /** @defgroup FMC_Write_Operation FMC Write Operation 443 * @{ 444 */ 445 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 446 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 447 /** 448 * @} 449 */ 450 451 /** @defgroup FMC_Wait_Signal FMC Wait Signal 452 * @{ 453 */ 454 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 455 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 456 /** 457 * @} 458 */ 459 460 /** @defgroup FMC_Extended_Mode FMC Extended Mode 461 * @{ 462 */ 463 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 464 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 465 /** 466 * @} 467 */ 468 469 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 470 * @{ 471 */ 472 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 473 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 474 /** 475 * @} 476 */ 477 478 /** @defgroup FMC_Page_Size FMC Page Size 479 * @{ 480 */ 481 #define FMC_PAGE_SIZE_NONE (0x00000000U) 482 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 483 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 484 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 485 | FMC_BCRx_CPSIZE_1) 486 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 487 /** 488 * @} 489 */ 490 491 /** @defgroup FMC_Write_Burst FMC Write Burst 492 * @{ 493 */ 494 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 495 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 496 /** 497 * @} 498 */ 499 500 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 501 * @{ 502 */ 503 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 504 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 505 /** 506 * @} 507 */ 508 509 #if defined(FMC_BCR1_WFDIS) 510 /** @defgroup FMC_Write_FIFO FMC Write FIFO 511 * @{ 512 */ 513 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 514 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 515 #endif /* FMC_BCR1_WFDIS */ 516 /** 517 * @} 518 */ 519 520 /** @defgroup FMC_Access_Mode FMC Access Mode 521 * @{ 522 */ 523 #define FMC_ACCESS_MODE_A (0x00000000U) 524 #define FMC_ACCESS_MODE_B (0x10000000U) 525 #define FMC_ACCESS_MODE_C (0x20000000U) 526 #define FMC_ACCESS_MODE_D (0x30000000U) 527 /** 528 * @} 529 */ 530 531 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 532 * @{ 533 */ 534 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 535 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 536 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 537 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 538 /** 539 * @} 540 */ 541 542 /** 543 * @} 544 */ 545 #endif /* FMC_BANK1 */ 546 547 #if defined(FMC_BANK3) 548 549 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 550 * @{ 551 */ 552 /** @defgroup FMC_NAND_Bank FMC NAND Bank 553 * @{ 554 */ 555 #define FMC_NAND_BANK3 (0x00000100U) 556 /** 557 * @} 558 */ 559 560 /** @defgroup FMC_Wait_feature FMC Wait feature 561 * @{ 562 */ 563 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 564 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 565 /** 566 * @} 567 */ 568 569 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 570 * @{ 571 */ 572 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 573 /** 574 * @} 575 */ 576 577 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 578 * @{ 579 */ 580 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 581 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 582 /** 583 * @} 584 */ 585 586 /** @defgroup FMC_ECC FMC ECC 587 * @{ 588 */ 589 #define FMC_NAND_ECC_DISABLE (0x00000000U) 590 #define FMC_NAND_ECC_ENABLE (0x00000040U) 591 /** 592 * @} 593 */ 594 595 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 596 * @{ 597 */ 598 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 599 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 600 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 601 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 602 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 603 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 604 /** 605 * @} 606 */ 607 608 /** 609 * @} 610 */ 611 #endif /* FMC_BANK3 */ 612 613 614 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 615 * @{ 616 */ 617 #if defined(FMC_BANK3) 618 #define FMC_IT_RISING_EDGE (0x00000008U) 619 #define FMC_IT_LEVEL (0x00000010U) 620 #define FMC_IT_FALLING_EDGE (0x00000020U) 621 #endif /* FMC_BANK3 */ 622 /** 623 * @} 624 */ 625 626 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 627 * @{ 628 */ 629 #if defined(FMC_BANK3) 630 #define FMC_FLAG_RISING_EDGE (0x00000001U) 631 #define FMC_FLAG_LEVEL (0x00000002U) 632 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 633 #define FMC_FLAG_FEMPT (0x00000040U) 634 #endif /* FMC_BANK3 */ 635 /** 636 * @} 637 */ 638 639 /** 640 * @} 641 */ 642 643 /** 644 * @} 645 */ 646 647 /* Private macro -------------------------------------------------------------*/ 648 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 649 * @{ 650 */ 651 #if defined(FMC_BANK1) 652 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 653 * @brief macros to handle NOR device enable/disable and read/write operations 654 * @{ 655 */ 656 657 /** 658 * @brief Enable the NORSRAM device access. 659 * @param __INSTANCE__ FMC_NORSRAM Instance 660 * @param __BANK__ FMC_NORSRAM Bank 661 * @retval None 662 */ 663 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 664 |= FMC_BCRx_MBKEN) 665 666 /** 667 * @brief Disable the NORSRAM device access. 668 * @param __INSTANCE__ FMC_NORSRAM Instance 669 * @param __BANK__ FMC_NORSRAM Bank 670 * @retval None 671 */ 672 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 673 &= ~FMC_BCRx_MBKEN) 674 675 /** 676 * @} 677 */ 678 #endif /* FMC_BANK1 */ 679 680 #if defined(FMC_BANK3) 681 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 682 * @brief macros to handle NAND device enable/disable 683 * @{ 684 */ 685 686 /** 687 * @brief Enable the NAND device access. 688 * @param __INSTANCE__ FMC_NAND Instance 689 * @retval None 690 */ 691 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 692 693 /** 694 * @brief Disable the NAND device access. 695 * @param __INSTANCE__ FMC_NAND Instance 696 * @param __BANK__ FMC_NAND Bank 697 * @retval None 698 */ 699 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 700 701 /** 702 * @} 703 */ 704 #endif /* FMC_BANK3 */ 705 706 #if defined(FMC_BANK3) 707 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 708 * @brief macros to handle NAND interrupts 709 * @{ 710 */ 711 712 /** 713 * @brief Enable the NAND device interrupt. 714 * @param __INSTANCE__ FMC_NAND instance 715 * @param __INTERRUPT__ FMC_NAND interrupt 716 * This parameter can be any combination of the following values: 717 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 718 * @arg FMC_IT_LEVEL: Interrupt level. 719 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 720 * @retval None 721 */ 722 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 723 724 /** 725 * @brief Disable the NAND device interrupt. 726 * @param __INSTANCE__ FMC_NAND Instance 727 * @param __INTERRUPT__ FMC_NAND interrupt 728 * This parameter can be any combination of the following values: 729 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 730 * @arg FMC_IT_LEVEL: Interrupt level. 731 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 732 * @retval None 733 */ 734 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 735 736 /** 737 * @brief Get flag status of the NAND device. 738 * @param __INSTANCE__ FMC_NAND Instance 739 * @param __BANK__ FMC_NAND Bank 740 * @param __FLAG__ FMC_NAND flag 741 * This parameter can be any combination of the following values: 742 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 743 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 744 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 745 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 746 * @retval The state of FLAG (SET or RESET). 747 */ 748 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 749 750 /** 751 * @brief Clear flag status of the NAND device. 752 * @param __INSTANCE__ FMC_NAND Instance 753 * @param __FLAG__ FMC_NAND flag 754 * This parameter can be any combination of the following values: 755 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 756 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 757 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 758 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 759 * @retval None 760 */ 761 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 762 763 /** 764 * @} 765 */ 766 #endif /* FMC_BANK3 */ 767 768 769 /** 770 * @} 771 */ 772 773 /** 774 * @} 775 */ 776 777 /* Private functions ---------------------------------------------------------*/ 778 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 779 * @{ 780 */ 781 782 #if defined(FMC_BANK1) 783 /** @defgroup FMC_LL_NORSRAM NOR SRAM 784 * @{ 785 */ 786 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 787 * @{ 788 */ 789 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 790 FMC_NORSRAM_InitTypeDef *Init); 791 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 792 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 793 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 794 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 795 uint32_t ExtendedMode); 796 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 797 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 798 /** 799 * @} 800 */ 801 802 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 803 * @{ 804 */ 805 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 806 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 807 /** 808 * @} 809 */ 810 /** 811 * @} 812 */ 813 #endif /* FMC_BANK1 */ 814 815 #if defined(FMC_BANK3) 816 /** @defgroup FMC_LL_NAND NAND 817 * @{ 818 */ 819 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 820 * @{ 821 */ 822 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 823 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 824 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 825 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 826 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 827 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 828 /** 829 * @} 830 */ 831 832 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 833 * @{ 834 */ 835 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 836 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 837 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 838 uint32_t Timeout); 839 /** 840 * @} 841 */ 842 /** 843 * @} 844 */ 845 #endif /* FMC_BANK3 */ 846 847 848 849 /** 850 * @} 851 */ 852 853 /** 854 * @} 855 */ 856 857 /** 858 * @} 859 */ 860 861 #ifdef __cplusplus 862 } 863 #endif 864 865 #endif /* STM32L4xx_LL_FMC_H */ 866
