1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_LL_FMC_H 21 #define STM32G4xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_BANK1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 60 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 61 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 62 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 63 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 64 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 65 ((__MODE__) == FMC_ACCESS_MODE_D)) 66 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 67 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 68 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 69 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 70 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 71 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 72 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 73 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 74 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 75 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 76 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 77 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 78 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 79 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 80 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 81 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 82 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 83 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 84 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 85 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 86 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 87 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 88 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 89 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 91 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 92 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 93 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 95 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 96 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 97 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 98 99 #endif /* FMC_BANK1 */ 100 #if defined(FMC_BANK3) 101 102 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 103 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 104 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 105 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 106 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 107 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 108 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 109 110 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 113 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 114 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 116 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 117 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 118 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 120 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 121 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 122 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 123 124 #endif /* FMC_BANK3 */ 125 126 /** 127 * @} 128 */ 129 130 /* Exported typedef ----------------------------------------------------------*/ 131 132 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 133 * @{ 134 */ 135 136 #if defined(FMC_BANK1) 137 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 138 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 139 #endif /* FMC_BANK1 */ 140 #if defined(FMC_BANK3) 141 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 142 #endif /* FMC_BANK3 */ 143 144 #if defined(FMC_BANK1) 145 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 146 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 147 #endif /* FMC_BANK1 */ 148 #if defined(FMC_BANK3) 149 #define FMC_NAND_DEVICE FMC_Bank3_R 150 #endif /* FMC_BANK3 */ 151 152 #if defined(FMC_BANK1) 153 /** 154 * @brief FMC NORSRAM Configuration Structure definition 155 */ 156 typedef struct 157 { 158 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 159 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 160 161 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 162 multiplexed on the data bus or not. 163 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 164 165 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 166 the corresponding memory device. 167 This parameter can be a value of @ref FMC_Memory_Type */ 168 169 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 170 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 171 172 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 173 valid only with synchronous burst Flash memories. 174 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 175 176 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 177 the Flash memory in burst mode. 178 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 179 180 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 181 clock cycle before the wait state or during the wait state, 182 valid only when accessing memories in burst mode. 183 This parameter can be a value of @ref FMC_Wait_Timing */ 184 185 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 186 This parameter can be a value of @ref FMC_Write_Operation */ 187 188 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 189 signal, valid for Flash memory access in burst mode. 190 This parameter can be a value of @ref FMC_Wait_Signal */ 191 192 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 193 This parameter can be a value of @ref FMC_Extended_Mode */ 194 195 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 196 valid only with asynchronous Flash memories. 197 This parameter can be a value of @ref FMC_AsynchronousWait */ 198 199 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 200 This parameter can be a value of @ref FMC_Write_Burst */ 201 202 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 203 This parameter is only enabled through the FMC_BCR1 register, 204 and don't care through FMC_BCR2..4 registers. 205 This parameter can be a value of @ref FMC_Continous_Clock */ 206 207 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 208 This parameter is only enabled through the FMC_BCR1 register, 209 and don't care through FMC_BCR2..4 registers. 210 This parameter can be a value of @ref FMC_Write_FIFO */ 211 212 uint32_t PageSize; /*!< Specifies the memory page size. 213 This parameter can be a value of @ref FMC_Page_Size */ 214 215 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 216 This parameter can be a value of @ref FMC_Byte_Lane */ 217 218 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 219 NSBank for PSRAM refresh. 220 This parameter can be set to ENABLE or DISABLE */ 221 222 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 223 synchronous accesses and in HCLK cycles for asynchronous accesses, 224 valid only if MaxChipSelectPulse is ENABLE. 225 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 226 @note: This parameter is common to all NSBank. */ 227 } FMC_NORSRAM_InitTypeDef; 228 229 /** 230 * @brief FMC NORSRAM Timing parameters structure definition 231 */ 232 typedef struct 233 { 234 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 235 the duration of the address setup time. 236 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 237 @note This parameter is not used with synchronous NOR Flash memories. */ 238 239 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 240 the duration of the address hold time. 241 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 242 @note This parameter is not used with synchronous NOR Flash memories. */ 243 244 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 245 the duration of the data setup time. 246 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 247 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 248 NOR Flash memories. */ 249 250 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 251 the duration of the data hold time. 252 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 253 @note This parameter is used for used in asynchronous accesses. */ 254 255 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 256 the duration of the bus turnaround. 257 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 258 @note This parameter is only used for multiplexed NOR Flash memories. */ 259 260 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 261 HCLK cycles. This parameter can be a value between Min_Data = 2 and 262 Max_Data = 16. 263 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 264 accesses. */ 265 266 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 267 to the memory before getting the first data. 268 The parameter value depends on the memory type as shown below: 269 - It must be set to 0 in case of a CRAM 270 - It is don't care in asynchronous NOR, SRAM or ROM accesses 271 - It may assume a value between Min_Data = 2 and Max_Data = 17 272 in NOR Flash memories with synchronous burst mode enable */ 273 274 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 275 This parameter can be a value of @ref FMC_Access_Mode */ 276 } FMC_NORSRAM_TimingTypeDef; 277 #endif /* FMC_BANK1 */ 278 279 #if defined(FMC_BANK3) 280 /** 281 * @brief FMC NAND Configuration Structure definition 282 */ 283 typedef struct 284 { 285 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 286 This parameter can be a value of @ref FMC_NAND_Bank */ 287 288 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 289 This parameter can be any value of @ref FMC_Wait_feature */ 290 291 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 292 This parameter can be any value of @ref FMC_NAND_Data_Width */ 293 294 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 295 This parameter can be any value of @ref FMC_ECC */ 296 297 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 298 This parameter can be any value of @ref FMC_ECC_Page_Size */ 299 300 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 301 delay between CLE low and RE low. 302 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 303 304 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 305 delay between ALE low and RE low. 306 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 307 } FMC_NAND_InitTypeDef; 308 #endif 309 310 #if defined(FMC_BANK3) 311 /** 312 * @brief FMC NAND Timing parameters structure definition 313 */ 314 typedef struct 315 { 316 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 317 the command assertion for NAND-Flash read or write access 318 to common/Attribute or I/O memory space (depending on 319 the memory space timing to be configured). 320 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 321 322 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 323 command for NAND-Flash read or write access to 324 common/Attribute or I/O memory space (depending on the 325 memory space timing to be configured). 326 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 327 328 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 329 (and data for write access) after the command de-assertion 330 for NAND-Flash read or write access to common/Attribute 331 or I/O memory space (depending on the memory space timing 332 to be configured). 333 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 334 335 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 336 data bus is kept in HiZ after the start of a NAND-Flash 337 write access to common/Attribute or I/O memory space (depending 338 on the memory space timing to be configured). 339 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 340 } FMC_NAND_PCC_TimingTypeDef; 341 #endif /* FMC_BANK3 */ 342 343 344 /** 345 * @} 346 */ 347 348 /* Exported constants --------------------------------------------------------*/ 349 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 350 * @{ 351 */ 352 #if defined(FMC_BANK1) 353 354 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 355 * @{ 356 */ 357 358 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 359 * @{ 360 */ 361 #define FMC_NORSRAM_BANK1 (0x00000000U) 362 #define FMC_NORSRAM_BANK2 (0x00000002U) 363 #define FMC_NORSRAM_BANK3 (0x00000004U) 364 #define FMC_NORSRAM_BANK4 (0x00000006U) 365 /** 366 * @} 367 */ 368 369 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 370 * @{ 371 */ 372 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 373 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 374 /** 375 * @} 376 */ 377 378 /** @defgroup FMC_Memory_Type FMC Memory Type 379 * @{ 380 */ 381 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 382 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 383 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 384 /** 385 * @} 386 */ 387 388 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 389 * @{ 390 */ 391 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 392 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 393 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 394 /** 395 * @} 396 */ 397 398 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 399 * @{ 400 */ 401 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 402 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 403 /** 404 * @} 405 */ 406 407 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 408 * @{ 409 */ 410 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 411 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 412 /** 413 * @} 414 */ 415 416 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 417 * @{ 418 */ 419 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 420 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 421 /** 422 * @} 423 */ 424 425 /** @defgroup FMC_Wait_Timing FMC Wait Timing 426 * @{ 427 */ 428 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 429 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 430 /** 431 * @} 432 */ 433 434 /** @defgroup FMC_Write_Operation FMC Write Operation 435 * @{ 436 */ 437 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 438 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 439 /** 440 * @} 441 */ 442 443 /** @defgroup FMC_Wait_Signal FMC Wait Signal 444 * @{ 445 */ 446 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 447 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 448 /** 449 * @} 450 */ 451 452 /** @defgroup FMC_Extended_Mode FMC Extended Mode 453 * @{ 454 */ 455 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 456 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 457 /** 458 * @} 459 */ 460 461 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 462 * @{ 463 */ 464 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 465 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 466 /** 467 * @} 468 */ 469 470 /** @defgroup FMC_Page_Size FMC Page Size 471 * @{ 472 */ 473 #define FMC_PAGE_SIZE_NONE (0x00000000U) 474 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 475 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 476 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 477 | FMC_BCRx_CPSIZE_1) 478 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 479 /** 480 * @} 481 */ 482 483 /** @defgroup FMC_Write_Burst FMC Write Burst 484 * @{ 485 */ 486 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 487 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 488 /** 489 * @} 490 */ 491 492 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 493 * @{ 494 */ 495 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 496 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 497 /** 498 * @} 499 */ 500 501 /** @defgroup FMC_Write_FIFO FMC Write FIFO 502 * @{ 503 */ 504 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 505 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 506 /** 507 * @} 508 */ 509 510 /** @defgroup FMC_Access_Mode FMC Access Mode 511 * @{ 512 */ 513 #define FMC_ACCESS_MODE_A (0x00000000U) 514 #define FMC_ACCESS_MODE_B (0x10000000U) 515 #define FMC_ACCESS_MODE_C (0x20000000U) 516 #define FMC_ACCESS_MODE_D (0x30000000U) 517 /** 518 * @} 519 */ 520 521 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 522 * @{ 523 */ 524 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 525 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 526 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 527 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 528 /** 529 * @} 530 */ 531 532 /** 533 * @} 534 */ 535 #endif /* FMC_BANK1 */ 536 537 #if defined(FMC_BANK3) 538 539 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 540 * @{ 541 */ 542 /** @defgroup FMC_NAND_Bank FMC NAND Bank 543 * @{ 544 */ 545 #define FMC_NAND_BANK3 (0x00000100U) 546 /** 547 * @} 548 */ 549 550 /** @defgroup FMC_Wait_feature FMC Wait feature 551 * @{ 552 */ 553 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 554 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 555 /** 556 * @} 557 */ 558 559 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 560 * @{ 561 */ 562 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 563 /** 564 * @} 565 */ 566 567 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 568 * @{ 569 */ 570 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 571 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 572 /** 573 * @} 574 */ 575 576 /** @defgroup FMC_ECC FMC ECC 577 * @{ 578 */ 579 #define FMC_NAND_ECC_DISABLE (0x00000000U) 580 #define FMC_NAND_ECC_ENABLE (0x00000040U) 581 /** 582 * @} 583 */ 584 585 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 586 * @{ 587 */ 588 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 589 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 590 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 591 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 592 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 593 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 594 /** 595 * @} 596 */ 597 598 /** 599 * @} 600 */ 601 #endif /* FMC_BANK3 */ 602 603 604 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 605 * @{ 606 */ 607 #if defined(FMC_BANK3) 608 #define FMC_IT_RISING_EDGE (0x00000008U) 609 #define FMC_IT_LEVEL (0x00000010U) 610 #define FMC_IT_FALLING_EDGE (0x00000020U) 611 #endif /* FMC_BANK3 */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 617 * @{ 618 */ 619 #if defined(FMC_BANK3) 620 #define FMC_FLAG_RISING_EDGE (0x00000001U) 621 #define FMC_FLAG_LEVEL (0x00000002U) 622 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 623 #define FMC_FLAG_FEMPT (0x00000040U) 624 #endif /* FMC_BANK3 */ 625 /** 626 * @} 627 */ 628 629 /** 630 * @} 631 */ 632 633 /** 634 * @} 635 */ 636 637 /* Private macro -------------------------------------------------------------*/ 638 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 639 * @{ 640 */ 641 #if defined(FMC_BANK1) 642 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 643 * @brief macros to handle NOR device enable/disable and read/write operations 644 * @{ 645 */ 646 647 /** 648 * @brief Enable the NORSRAM device access. 649 * @param __INSTANCE__ FMC_NORSRAM Instance 650 * @param __BANK__ FMC_NORSRAM Bank 651 * @retval None 652 */ 653 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 654 |= FMC_BCRx_MBKEN) 655 656 /** 657 * @brief Disable the NORSRAM device access. 658 * @param __INSTANCE__ FMC_NORSRAM Instance 659 * @param __BANK__ FMC_NORSRAM Bank 660 * @retval None 661 */ 662 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 663 &= ~FMC_BCRx_MBKEN) 664 665 /** 666 * @} 667 */ 668 #endif /* FMC_BANK1 */ 669 670 #if defined(FMC_BANK3) 671 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 672 * @brief macros to handle NAND device enable/disable 673 * @{ 674 */ 675 676 /** 677 * @brief Enable the NAND device access. 678 * @param __INSTANCE__ FMC_NAND Instance 679 * @retval None 680 */ 681 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 682 683 /** 684 * @brief Disable the NAND device access. 685 * @param __INSTANCE__ FMC_NAND Instance 686 * @param __BANK__ FMC_NAND Bank 687 * @retval None 688 */ 689 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 690 691 /** 692 * @} 693 */ 694 #endif 695 696 #if defined(FMC_BANK3) 697 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 698 * @brief macros to handle NAND interrupts 699 * @{ 700 */ 701 702 /** 703 * @brief Enable the NAND device interrupt. 704 * @param __INSTANCE__ FMC_NAND instance 705 * @param __INTERRUPT__ FMC_NAND interrupt 706 * This parameter can be any combination of the following values: 707 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 708 * @arg FMC_IT_LEVEL: Interrupt level. 709 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 710 * @retval None 711 */ 712 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 713 714 /** 715 * @brief Disable the NAND device interrupt. 716 * @param __INSTANCE__ FMC_NAND Instance 717 * @param __INTERRUPT__ FMC_NAND interrupt 718 * This parameter can be any combination of the following values: 719 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 720 * @arg FMC_IT_LEVEL: Interrupt level. 721 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 722 * @retval None 723 */ 724 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 725 726 /** 727 * @brief Get flag status of the NAND device. 728 * @param __INSTANCE__ FMC_NAND Instance 729 * @param __BANK__ FMC_NAND Bank 730 * @param __FLAG__ FMC_NAND flag 731 * This parameter can be any combination of the following values: 732 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 733 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 734 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 735 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 736 * @retval The state of FLAG (SET or RESET). 737 */ 738 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 739 740 /** 741 * @brief Clear flag status of the NAND device. 742 * @param __INSTANCE__ FMC_NAND Instance 743 * @param __FLAG__ FMC_NAND flag 744 * This parameter can be any combination of the following values: 745 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 746 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 747 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 748 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 749 * @retval None 750 */ 751 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 752 753 /** 754 * @} 755 */ 756 #endif /* FMC_BANK3 */ 757 758 759 /** 760 * @} 761 */ 762 763 /** 764 * @} 765 */ 766 767 /* Private functions ---------------------------------------------------------*/ 768 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 769 * @{ 770 */ 771 772 #if defined(FMC_BANK1) 773 /** @defgroup FMC_LL_NORSRAM NOR SRAM 774 * @{ 775 */ 776 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 777 * @{ 778 */ 779 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 780 FMC_NORSRAM_InitTypeDef *Init); 781 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 782 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 783 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 784 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 785 uint32_t ExtendedMode); 786 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 787 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 788 /** 789 * @} 790 */ 791 792 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 793 * @{ 794 */ 795 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 796 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 797 /** 798 * @} 799 */ 800 /** 801 * @} 802 */ 803 #endif /* FMC_BANK1 */ 804 805 #if defined(FMC_BANK3) 806 /** @defgroup FMC_LL_NAND NAND 807 * @{ 808 */ 809 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 810 * @{ 811 */ 812 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 813 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 814 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 815 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 816 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 817 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 818 /** 819 * @} 820 */ 821 822 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 823 * @{ 824 */ 825 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 826 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 827 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 828 uint32_t Timeout); 829 /** 830 * @} 831 */ 832 /** 833 * @} 834 */ 835 #endif /* FMC_BANK3 */ 836 837 838 839 /** 840 * @} 841 */ 842 843 /** 844 * @} 845 */ 846 847 /** 848 * @} 849 */ 850 851 #ifdef __cplusplus 852 } 853 #endif 854 855 #endif /* STM32G4xx_LL_FMC_H */ 856
