1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_LL_FMC_H 21 #define STM32F4xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_Bank1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 60 #if defined(FMC_BCR1_WFDIS) 61 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 62 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 63 #endif /* FMC_BCR1_WFDIS */ 64 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 65 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 66 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 67 ((__MODE__) == FMC_ACCESS_MODE_D)) 68 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 69 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 70 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 71 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 72 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ 73 ((__MODE__) == FMC_WRAP_MODE_ENABLE)) 74 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 75 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 76 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 77 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 78 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 79 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 80 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 81 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 82 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 83 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 84 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 85 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 86 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 87 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 88 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 89 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 91 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 92 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 93 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 95 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 96 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 97 98 #endif /* FMC_Bank1 */ 99 #if (defined(FMC_Bank3) || defined(FMC_Bank2_3)) 100 101 #if defined(FMC_Bank2_3) 102 #define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \ 103 ((__BANK__) == FMC_NAND_BANK3)) 104 #else 105 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 106 #endif /* FMC_Bank2_3 */ 107 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ 108 ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) 109 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ 110 ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) 111 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 112 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 113 114 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 116 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 117 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 118 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 119 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 120 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 121 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 122 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 123 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 124 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 125 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 126 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 127 128 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ 129 #if defined(FMC_Bank4) 130 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) 131 132 #endif /* FMC_Bank4 */ 133 #if defined(FMC_Bank5_6) 134 135 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ 136 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ 137 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) 138 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ 139 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 140 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ 141 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ 142 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 143 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ 144 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 145 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ 146 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ 147 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 148 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ 149 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ 150 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ 151 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ 152 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ 153 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ 154 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 155 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ 156 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ 157 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 158 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 159 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 160 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 161 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 162 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 163 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 164 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 165 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) 166 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) 167 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) 168 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 169 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ 170 ((__BANK__) == FMC_SDRAM_BANK2)) 171 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ 172 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ 173 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ 174 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 175 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ 176 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ 177 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) 178 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ 179 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 180 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ 181 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ 182 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) 183 184 #endif /* FMC_Bank5_6 */ 185 186 /** 187 * @} 188 */ 189 190 /* Exported typedef ----------------------------------------------------------*/ 191 192 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 193 * @{ 194 */ 195 196 #if defined(FMC_Bank1) 197 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 198 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 199 #endif /* FMC_Bank1 */ 200 #if defined(FMC_Bank2_3) 201 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef 202 #else 203 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 204 #endif /* FMC_Bank2_3 */ 205 #if defined(FMC_Bank4) 206 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef 207 #endif /* FMC_Bank4 */ 208 #if defined(FMC_Bank5_6) 209 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 210 #endif /* FMC_Bank5_6 */ 211 212 #if defined(FMC_Bank1) 213 #define FMC_NORSRAM_DEVICE FMC_Bank1 214 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E 215 #endif /* FMC_Bank1 */ 216 #if defined(FMC_Bank2_3) 217 #define FMC_NAND_DEVICE FMC_Bank2_3 218 #else 219 #define FMC_NAND_DEVICE FMC_Bank3 220 #endif /* FMC_Bank2_3 */ 221 #if defined(FMC_Bank4) 222 #define FMC_PCCARD_DEVICE FMC_Bank4 223 #endif /* FMC_Bank4 */ 224 #if defined(FMC_Bank5_6) 225 #define FMC_SDRAM_DEVICE FMC_Bank5_6 226 #endif /* FMC_Bank5_6 */ 227 228 #if defined(FMC_Bank1) 229 /** 230 * @brief FMC NORSRAM Configuration Structure definition 231 */ 232 typedef struct 233 { 234 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 235 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 236 237 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 238 multiplexed on the data bus or not. 239 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 240 241 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 242 the corresponding memory device. 243 This parameter can be a value of @ref FMC_Memory_Type */ 244 245 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 246 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 247 248 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 249 valid only with synchronous burst Flash memories. 250 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 251 252 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 253 the Flash memory in burst mode. 254 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 255 256 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 257 memory, valid only when accessing Flash memories in burst mode. 258 This parameter can be a value of @ref FMC_Wrap_Mode 259 This mode is not available for the STM32F446/467/479xx devices */ 260 261 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 262 clock cycle before the wait state or during the wait state, 263 valid only when accessing memories in burst mode. 264 This parameter can be a value of @ref FMC_Wait_Timing */ 265 266 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 267 This parameter can be a value of @ref FMC_Write_Operation */ 268 269 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 270 signal, valid for Flash memory access in burst mode. 271 This parameter can be a value of @ref FMC_Wait_Signal */ 272 273 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 274 This parameter can be a value of @ref FMC_Extended_Mode */ 275 276 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 277 valid only with asynchronous Flash memories. 278 This parameter can be a value of @ref FMC_AsynchronousWait */ 279 280 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 281 This parameter can be a value of @ref FMC_Write_Burst */ 282 283 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 284 This parameter is only enabled through the FMC_BCR1 register, 285 and don't care through FMC_BCR2..4 registers. 286 This parameter can be a value of @ref FMC_Continous_Clock */ 287 288 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 289 This parameter is only enabled through the FMC_BCR1 register, 290 and don't care through FMC_BCR2..4 registers. 291 This parameter can be a value of @ref FMC_Write_FIFO 292 This mode is available only for the STM32F446/469/479xx devices */ 293 294 uint32_t PageSize; /*!< Specifies the memory page size. 295 This parameter can be a value of @ref FMC_Page_Size */ 296 } FMC_NORSRAM_InitTypeDef; 297 298 /** 299 * @brief FMC NORSRAM Timing parameters structure definition 300 */ 301 typedef struct 302 { 303 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 304 the duration of the address setup time. 305 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 306 @note This parameter is not used with synchronous NOR Flash memories. */ 307 308 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 309 the duration of the address hold time. 310 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 311 @note This parameter is not used with synchronous NOR Flash memories. */ 312 313 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 314 the duration of the data setup time. 315 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 316 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 317 NOR Flash memories. */ 318 319 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 320 the duration of the bus turnaround. 321 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 322 @note This parameter is only used for multiplexed NOR Flash memories. */ 323 324 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 325 HCLK cycles. This parameter can be a value between Min_Data = 2 and 326 Max_Data = 16. 327 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 328 accesses. */ 329 330 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 331 to the memory before getting the first data. 332 The parameter value depends on the memory type as shown below: 333 - It must be set to 0 in case of a CRAM 334 - It is don't care in asynchronous NOR, SRAM or ROM accesses 335 - It may assume a value between Min_Data = 2 and Max_Data = 17 336 in NOR Flash memories with synchronous burst mode enable */ 337 338 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 339 This parameter can be a value of @ref FMC_Access_Mode */ 340 } FMC_NORSRAM_TimingTypeDef; 341 #endif /* FMC_Bank1 */ 342 343 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) 344 /** 345 * @brief FMC NAND Configuration Structure definition 346 */ 347 typedef struct 348 { 349 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 350 This parameter can be a value of @ref FMC_NAND_Bank */ 351 352 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 353 This parameter can be any value of @ref FMC_Wait_feature */ 354 355 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 356 This parameter can be any value of @ref FMC_NAND_Data_Width */ 357 358 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 359 This parameter can be any value of @ref FMC_ECC */ 360 361 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 362 This parameter can be any value of @ref FMC_ECC_Page_Size */ 363 364 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 365 delay between CLE low and RE low. 366 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 367 368 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 369 delay between ALE low and RE low. 370 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 371 } FMC_NAND_InitTypeDef; 372 #endif 373 374 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) 375 /** 376 * @brief FMC NAND Timing parameters structure definition 377 */ 378 typedef struct 379 { 380 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 381 the command assertion for NAND-Flash read or write access 382 to common/Attribute or I/O memory space (depending on 383 the memory space timing to be configured). 384 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 385 386 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 387 command for NAND-Flash read or write access to 388 common/Attribute or I/O memory space (depending on the 389 memory space timing to be configured). 390 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 391 392 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 393 (and data for write access) after the command de-assertion 394 for NAND-Flash read or write access to common/Attribute 395 or I/O memory space (depending on the memory space timing 396 to be configured). 397 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 398 399 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 400 data bus is kept in HiZ after the start of a NAND-Flash 401 write access to common/Attribute or I/O memory space (depending 402 on the memory space timing to be configured). 403 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 404 } FMC_NAND_PCC_TimingTypeDef; 405 #endif /* FMC_Bank3 || FMC_Bank2_3 */ 406 407 #if defined(FMC_Bank4) 408 /** 409 * @brief FMC PCCARD Configuration Structure definition 410 */ 411 typedef struct 412 { 413 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. 414 This parameter can be any value of @ref FMC_Wait_feature */ 415 416 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 417 delay between CLE low and RE low. 418 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 419 420 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 421 delay between ALE low and RE low. 422 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 423 }FMC_PCCARD_InitTypeDef; 424 #endif /* FMC_Bank4 */ 425 426 #if defined(FMC_Bank5_6) 427 /** 428 * @brief FMC SDRAM Configuration Structure definition 429 */ 430 typedef struct 431 { 432 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. 433 This parameter can be a value of @ref FMC_SDRAM_Bank */ 434 435 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. 436 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ 437 438 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. 439 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ 440 441 uint32_t MemoryDataWidth; /*!< Defines the memory device width. 442 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ 443 444 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. 445 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ 446 447 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. 448 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ 449 450 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. 451 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ 452 453 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 454 to disable the clock before changing frequency. 455 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ 456 457 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read 458 commands during the CAS latency and stores data in the Read FIFO. 459 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ 460 461 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. 462 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ 463 } FMC_SDRAM_InitTypeDef; 464 465 /** 466 * @brief FMC SDRAM Timing parameters structure definition 467 */ 468 typedef struct 469 { 470 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and 471 an active or Refresh command in number of memory clock cycles. 472 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 473 474 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to 475 issuing the Activate command in number of memory clock cycles. 476 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 477 478 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock 479 cycles. 480 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 481 482 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command 483 and the delay between two consecutive Refresh commands in number of 484 memory clock cycles. 485 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 486 487 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. 488 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 489 490 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command 491 in number of memory clock cycles. 492 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 493 494 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write 495 command in number of memory clock cycles. 496 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 497 } FMC_SDRAM_TimingTypeDef; 498 499 /** 500 * @brief SDRAM command parameters structure definition 501 */ 502 typedef struct 503 { 504 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. 505 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ 506 507 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. 508 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ 509 510 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued 511 in auto refresh mode. 512 This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ 513 514 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ 515 } FMC_SDRAM_CommandTypeDef; 516 #endif /* FMC_Bank5_6 */ 517 /** 518 * @} 519 */ 520 521 /* Exported constants --------------------------------------------------------*/ 522 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 523 * @{ 524 */ 525 #if defined(FMC_Bank1) 526 527 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 528 * @{ 529 */ 530 531 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 532 * @{ 533 */ 534 #define FMC_NORSRAM_BANK1 (0x00000000U) 535 #define FMC_NORSRAM_BANK2 (0x00000002U) 536 #define FMC_NORSRAM_BANK3 (0x00000004U) 537 #define FMC_NORSRAM_BANK4 (0x00000006U) 538 /** 539 * @} 540 */ 541 542 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 543 * @{ 544 */ 545 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 546 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 547 /** 548 * @} 549 */ 550 551 /** @defgroup FMC_Memory_Type FMC Memory Type 552 * @{ 553 */ 554 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 555 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 556 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 557 /** 558 * @} 559 */ 560 561 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 562 * @{ 563 */ 564 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 565 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 566 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 567 /** 568 * @} 569 */ 570 571 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 572 * @{ 573 */ 574 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 575 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 576 /** 577 * @} 578 */ 579 580 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 581 * @{ 582 */ 583 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 584 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 585 /** 586 * @} 587 */ 588 589 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 590 * @{ 591 */ 592 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 593 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 594 /** 595 * @} 596 */ 597 598 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode 599 * @note This mode is not available for the STM32F446/469/479xx devices 600 * @{ 601 */ 602 #define FMC_WRAP_MODE_DISABLE (0x00000000U) 603 #define FMC_WRAP_MODE_ENABLE (0x00000400U) 604 /** 605 * @} 606 */ 607 608 /** @defgroup FMC_Wait_Timing FMC Wait Timing 609 * @{ 610 */ 611 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 612 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 613 /** 614 * @} 615 */ 616 617 /** @defgroup FMC_Write_Operation FMC Write Operation 618 * @{ 619 */ 620 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 621 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 622 /** 623 * @} 624 */ 625 626 /** @defgroup FMC_Wait_Signal FMC Wait Signal 627 * @{ 628 */ 629 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 630 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 631 /** 632 * @} 633 */ 634 635 /** @defgroup FMC_Extended_Mode FMC Extended Mode 636 * @{ 637 */ 638 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 639 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 640 /** 641 * @} 642 */ 643 644 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 645 * @{ 646 */ 647 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 648 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 649 /** 650 * @} 651 */ 652 653 /** @defgroup FMC_Page_Size FMC Page Size 654 * @{ 655 */ 656 #define FMC_PAGE_SIZE_NONE (0x00000000U) 657 #define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0 658 #define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1 659 #define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\ 660 | FMC_BCR1_CPSIZE_1) 661 #define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2 662 /** 663 * @} 664 */ 665 666 /** @defgroup FMC_Write_Burst FMC Write Burst 667 * @{ 668 */ 669 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 670 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 671 /** 672 * @} 673 */ 674 675 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 676 * @{ 677 */ 678 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 679 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 680 /** 681 * @} 682 */ 683 684 #if defined(FMC_BCR1_WFDIS) 685 /** @defgroup FMC_Write_FIFO FMC Write FIFO 686 * @note These values are available only for the STM32F446/469/479xx devices. 687 * @{ 688 */ 689 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 690 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 691 #endif /* FMC_BCR1_WFDIS */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup FMC_Access_Mode FMC Access Mode 697 * @{ 698 */ 699 #define FMC_ACCESS_MODE_A (0x00000000U) 700 #define FMC_ACCESS_MODE_B (0x10000000U) 701 #define FMC_ACCESS_MODE_C (0x20000000U) 702 #define FMC_ACCESS_MODE_D (0x30000000U) 703 /** 704 * @} 705 */ 706 707 /** 708 * @} 709 */ 710 #endif /* FMC_Bank1 */ 711 712 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) 713 714 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 715 * @{ 716 */ 717 /** @defgroup FMC_NAND_Bank FMC NAND Bank 718 * @{ 719 */ 720 #if defined(FMC_Bank2_3) 721 #define FMC_NAND_BANK2 (0x00000010U) 722 #endif 723 #define FMC_NAND_BANK3 (0x00000100U) 724 /** 725 * @} 726 */ 727 728 /** @defgroup FMC_Wait_feature FMC Wait feature 729 * @{ 730 */ 731 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) 732 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) 733 /** 734 * @} 735 */ 736 737 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 738 * @{ 739 */ 740 #if defined(FMC_Bank4) 741 #define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) 742 #endif /* FMC_Bank4 */ 743 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 744 /** 745 * @} 746 */ 747 748 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 749 * @{ 750 */ 751 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) 752 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) 753 /** 754 * @} 755 */ 756 757 /** @defgroup FMC_ECC FMC ECC 758 * @{ 759 */ 760 #define FMC_NAND_ECC_DISABLE (0x00000000U) 761 #define FMC_NAND_ECC_ENABLE (0x00000040U) 762 /** 763 * @} 764 */ 765 766 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 767 * @{ 768 */ 769 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 770 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 771 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 772 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 773 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 774 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 775 /** 776 * @} 777 */ 778 779 /** 780 * @} 781 */ 782 #endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ 783 784 #if defined(FMC_Bank5_6) 785 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 786 * @{ 787 */ 788 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank 789 * @{ 790 */ 791 #define FMC_SDRAM_BANK1 (0x00000000U) 792 #define FMC_SDRAM_BANK2 (0x00000001U) 793 /** 794 * @} 795 */ 796 797 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 798 * @{ 799 */ 800 #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) 801 #define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) 802 #define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) 803 #define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) 804 /** 805 * @} 806 */ 807 808 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number 809 * @{ 810 */ 811 #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) 812 #define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) 813 #define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) 814 /** 815 * @} 816 */ 817 818 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width 819 * @{ 820 */ 821 #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) 822 #define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) 823 #define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) 824 /** 825 * @} 826 */ 827 828 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number 829 * @{ 830 */ 831 #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) 832 #define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) 833 /** 834 * @} 835 */ 836 837 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency 838 * @{ 839 */ 840 #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) 841 #define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) 842 #define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) 843 /** 844 * @} 845 */ 846 847 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection 848 * @{ 849 */ 850 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) 851 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) 852 /** 853 * @} 854 */ 855 856 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period 857 * @{ 858 */ 859 #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) 860 #define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) 861 #define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) 862 /** 863 * @} 864 */ 865 866 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst 867 * @{ 868 */ 869 #define FMC_SDRAM_RBURST_DISABLE (0x00000000U) 870 #define FMC_SDRAM_RBURST_ENABLE (0x00001000U) 871 /** 872 * @} 873 */ 874 875 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay 876 * @{ 877 */ 878 #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) 879 #define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) 880 #define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) 881 /** 882 * @} 883 */ 884 885 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode 886 * @{ 887 */ 888 #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) 889 #define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) 890 #define FMC_SDRAM_CMD_PALL (0x00000002U) 891 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) 892 #define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) 893 #define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) 894 #define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) 895 /** 896 * @} 897 */ 898 899 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target 900 * @{ 901 */ 902 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 903 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 904 #define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) 905 /** 906 * @} 907 */ 908 909 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 910 * @{ 911 */ 912 #define FMC_SDRAM_NORMAL_MODE (0x00000000U) 913 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 914 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 915 /** 916 * @} 917 */ 918 919 /** 920 * @} 921 */ 922 923 #endif /* FMC_Bank5_6 */ 924 925 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 926 * @{ 927 */ 928 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) 929 #define FMC_IT_RISING_EDGE (0x00000008U) 930 #define FMC_IT_LEVEL (0x00000010U) 931 #define FMC_IT_FALLING_EDGE (0x00000020U) 932 #endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ 933 #if defined(FMC_Bank5_6) 934 #define FMC_IT_REFRESH_ERROR (0x00004000U) 935 #endif /* FMC_Bank5_6 */ 936 /** 937 * @} 938 */ 939 940 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 941 * @{ 942 */ 943 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) 944 #define FMC_FLAG_RISING_EDGE (0x00000001U) 945 #define FMC_FLAG_LEVEL (0x00000002U) 946 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 947 #define FMC_FLAG_FEMPT (0x00000040U) 948 #endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ 949 #if defined(FMC_Bank5_6) 950 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 951 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 952 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 953 #endif /* FMC_Bank5_6 */ 954 /** 955 * @} 956 */ 957 958 /** 959 * @} 960 */ 961 962 /** 963 * @} 964 */ 965 966 /* Private macro -------------------------------------------------------------*/ 967 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 968 * @{ 969 */ 970 #if defined(FMC_Bank1) 971 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 972 * @brief macros to handle NOR device enable/disable and read/write operations 973 * @{ 974 */ 975 976 /** 977 * @brief Enable the NORSRAM device access. 978 * @param __INSTANCE__ FMC_NORSRAM Instance 979 * @param __BANK__ FMC_NORSRAM Bank 980 * @retval None 981 */ 982 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 983 |= FMC_BCR1_MBKEN) 984 985 /** 986 * @brief Disable the NORSRAM device access. 987 * @param __INSTANCE__ FMC_NORSRAM Instance 988 * @param __BANK__ FMC_NORSRAM Bank 989 * @retval None 990 */ 991 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 992 &= ~FMC_BCR1_MBKEN) 993 994 /** 995 * @} 996 */ 997 #endif /* FMC_Bank1 */ 998 999 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) 1000 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 1001 * @brief macros to handle NAND device enable/disable 1002 * @{ 1003 */ 1004 1005 /** 1006 * @brief Enable the NAND device access. 1007 * @param __INSTANCE__ FMC_NAND Instance 1008 * @param __BANK__ FMC_NAND Bank 1009 * @retval None 1010 */ 1011 #if defined(FMC_Bank2_3) 1012 #if defined (FMC_PCR_PBKEN) 1013 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 1014 #else 1015 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \ 1016 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) 1017 #endif /* FMC_PCR_PBKEN */ 1018 #else 1019 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 1020 #endif /* FMC_Bank2_3 */ 1021 1022 /** 1023 * @brief Disable the NAND device access. 1024 * @param __INSTANCE__ FMC_NAND Instance 1025 * @param __BANK__ FMC_NAND Bank 1026 * @retval None 1027 */ 1028 #if defined(FMC_Bank2_3) 1029 #if defined (FMC_PCR_PBKEN) 1030 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 1031 #else 1032 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCR2_PBKEN): \ 1033 CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCR3_PBKEN)) 1034 #endif /* FMC_PCR_PBKEN */ 1035 #else 1036 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 1037 #endif /* FMC_Bank2_3 */ 1038 1039 /** 1040 * @} 1041 */ 1042 #endif /* FMC_Bank3 || FMC_Bank2_3 */ 1043 1044 #if defined(FMC_Bank4) 1045 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros 1046 * @brief macros to handle PCCARD read/write operations 1047 * @{ 1048 */ 1049 /** 1050 * @brief Enable the PCCARD device access. 1051 * @param __INSTANCE__ FMC_PCCARD Instance 1052 * @retval None 1053 */ 1054 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN) 1055 1056 /** 1057 * @brief Disable the PCCARD device access. 1058 * @param __INSTANCE__ FMC_PCCARD Instance 1059 * @retval None 1060 */ 1061 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN) 1062 /** 1063 * @} 1064 */ 1065 1066 #endif 1067 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) 1068 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 1069 * @brief macros to handle NAND interrupts 1070 * @{ 1071 */ 1072 1073 /** 1074 * @brief Enable the NAND device interrupt. 1075 * @param __INSTANCE__ FMC_NAND instance 1076 * @param __BANK__ FMC_NAND Bank 1077 * @param __INTERRUPT__ FMC_NAND interrupt 1078 * This parameter can be any combination of the following values: 1079 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1080 * @arg FMC_IT_LEVEL: Interrupt level. 1081 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1082 * @retval None 1083 */ 1084 #if defined(FMC_Bank2_3) 1085 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ 1086 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) 1087 #else 1088 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 1089 #endif /* FMC_Bank2_3 */ 1090 1091 /** 1092 * @brief Disable the NAND device interrupt. 1093 * @param __INSTANCE__ FMC_NAND Instance 1094 * @param __BANK__ FMC_NAND Bank 1095 * @param __INTERRUPT__ FMC_NAND interrupt 1096 * This parameter can be any combination of the following values: 1097 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1098 * @arg FMC_IT_LEVEL: Interrupt level. 1099 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1100 * @retval None 1101 */ 1102 #if defined(FMC_Bank2_3) 1103 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ 1104 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 1105 #else 1106 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 1107 #endif /* FMC_Bank2_3 */ 1108 1109 /** 1110 * @brief Get flag status of the NAND device. 1111 * @param __INSTANCE__ FMC_NAND Instance 1112 * @param __BANK__ FMC_NAND Bank 1113 * @param __FLAG__ FMC_NAND flag 1114 * This parameter can be any combination of the following values: 1115 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1116 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1117 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1118 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1119 * @retval The state of FLAG (SET or RESET). 1120 */ 1121 #if defined(FMC_Bank2_3) 1122 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ 1123 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) 1124 #else 1125 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 1126 #endif /* FMC_Bank2_3 */ 1127 1128 /** 1129 * @brief Clear flag status of the NAND device. 1130 * @param __INSTANCE__ FMC_NAND Instance 1131 * @param __BANK__ FMC_NAND Bank 1132 * @param __FLAG__ FMC_NAND flag 1133 * This parameter can be any combination of the following values: 1134 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1135 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1136 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1137 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1138 * @retval None 1139 */ 1140 #if defined(FMC_Bank2_3) 1141 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ 1142 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 1143 #else 1144 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 1145 #endif /* FMC_Bank2_3 */ 1146 1147 /** 1148 * @} 1149 */ 1150 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ 1151 1152 #if defined(FMC_Bank4) 1153 /** @defgroup FMC_LL_PCCARD_Interrupt FMC PCCARD Interrupt 1154 * @brief macros to handle PCCARD interrupts 1155 * @{ 1156 */ 1157 1158 /** 1159 * @brief Enable the PCCARD device interrupt. 1160 * @param __INSTANCE__ FMC_PCCARD instance 1161 * @param __INTERRUPT__ FMC_PCCARD interrupt 1162 * This parameter can be any combination of the following values: 1163 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1164 * @arg FMC_IT_LEVEL: Interrupt level. 1165 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1166 * @retval None 1167 */ 1168 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) 1169 1170 /** 1171 * @brief Disable the PCCARD device interrupt. 1172 * @param __INSTANCE__ FMC_PCCARD instance 1173 * @param __INTERRUPT__ FMC_PCCARD interrupt 1174 * This parameter can be any combination of the following values: 1175 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1176 * @arg FMC_IT_LEVEL: Interrupt level. 1177 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1178 * @retval None 1179 */ 1180 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 1181 1182 /** 1183 * @brief Get flag status of the PCCARD device. 1184 * @param __INSTANCE__ FMC_PCCARD instance 1185 * @param __FLAG__ FMC_PCCARD flag 1186 * This parameter can be any combination of the following values: 1187 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1188 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1189 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1190 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1191 * @retval The state of FLAG (SET or RESET). 1192 */ 1193 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) 1194 1195 /** 1196 * @brief Clear flag status of the PCCARD device. 1197 * @param __INSTANCE__ FMC_PCCARD instance 1198 * @param __FLAG__ FMC_PCCARD flag 1199 * This parameter can be any combination of the following values: 1200 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1201 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1202 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1203 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1204 * @retval None 1205 */ 1206 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) 1207 1208 /** 1209 * @} 1210 */ 1211 #endif 1212 1213 #if defined(FMC_Bank5_6) 1214 /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt 1215 * @brief macros to handle SDRAM interrupts 1216 * @{ 1217 */ 1218 1219 /** 1220 * @brief Enable the SDRAM device interrupt. 1221 * @param __INSTANCE__ FMC_SDRAM instance 1222 * @param __INTERRUPT__ FMC_SDRAM interrupt 1223 * This parameter can be any combination of the following values: 1224 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1225 * @retval None 1226 */ 1227 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 1228 1229 /** 1230 * @brief Disable the SDRAM device interrupt. 1231 * @param __INSTANCE__ FMC_SDRAM instance 1232 * @param __INTERRUPT__ FMC_SDRAM interrupt 1233 * This parameter can be any combination of the following values: 1234 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1235 * @retval None 1236 */ 1237 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 1238 1239 /** 1240 * @brief Get flag status of the SDRAM device. 1241 * @param __INSTANCE__ FMC_SDRAM instance 1242 * @param __FLAG__ FMC_SDRAM flag 1243 * This parameter can be any combination of the following values: 1244 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. 1245 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. 1246 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. 1247 * @retval The state of FLAG (SET or RESET). 1248 */ 1249 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 1250 1251 /** 1252 * @brief Clear flag status of the SDRAM device. 1253 * @param __INSTANCE__ FMC_SDRAM instance 1254 * @param __FLAG__ FMC_SDRAM flag 1255 * This parameter can be any combination of the following values: 1256 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR 1257 * @retval None 1258 */ 1259 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 1260 1261 /** 1262 * @} 1263 */ 1264 #endif /* FMC_Bank5_6 */ 1265 /** 1266 * @} 1267 */ 1268 1269 /** 1270 * @} 1271 */ 1272 1273 /* Private functions ---------------------------------------------------------*/ 1274 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 1275 * @{ 1276 */ 1277 1278 #if defined(FMC_Bank1) 1279 /** @defgroup FMC_LL_NORSRAM NOR SRAM 1280 * @{ 1281 */ 1282 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 1283 * @{ 1284 */ 1285 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 1286 FMC_NORSRAM_InitTypeDef *Init); 1287 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 1288 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 1289 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 1290 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 1291 uint32_t ExtendedMode); 1292 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 1293 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1299 * @{ 1300 */ 1301 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1302 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1303 /** 1304 * @} 1305 */ 1306 /** 1307 * @} 1308 */ 1309 #endif /* FMC_Bank1 */ 1310 1311 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) 1312 /** @defgroup FMC_LL_NAND NAND 1313 * @{ 1314 */ 1315 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1316 * @{ 1317 */ 1318 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 1319 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1320 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1321 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1322 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1323 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 1324 /** 1325 * @} 1326 */ 1327 1328 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1329 * @{ 1330 */ 1331 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1332 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1333 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 1334 uint32_t Timeout); 1335 /** 1336 * @} 1337 */ 1338 /** 1339 * @} 1340 */ 1341 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ 1342 1343 #if defined(FMC_Bank4) 1344 /** @defgroup FMC_LL_PCCARD PCCARD 1345 * @{ 1346 */ 1347 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 1348 * @{ 1349 */ 1350 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); 1351 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, 1352 FMC_NAND_PCC_TimingTypeDef *Timing); 1353 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, 1354 FMC_NAND_PCC_TimingTypeDef *Timing); 1355 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, 1356 FMC_NAND_PCC_TimingTypeDef *Timing); 1357 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); 1358 /** 1359 * @} 1360 */ 1361 /** 1362 * @} 1363 */ 1364 #endif /* FMC_Bank4 */ 1365 1366 #if defined(FMC_Bank5_6) 1367 /** @defgroup FMC_LL_SDRAM SDRAM 1368 * @{ 1369 */ 1370 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 1371 * @{ 1372 */ 1373 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); 1374 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, 1375 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); 1376 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1377 /** 1378 * @} 1379 */ 1380 1381 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 1382 * @{ 1383 */ 1384 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1385 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1386 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, 1387 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); 1388 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); 1389 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, 1390 uint32_t AutoRefreshNumber); 1391 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1392 /** 1393 * @} 1394 */ 1395 /** 1396 * @} 1397 */ 1398 #endif /* FMC_Bank5_6 */ 1399 1400 /** 1401 * @} 1402 */ 1403 1404 /** 1405 * @} 1406 */ 1407 1408 /** 1409 * @} 1410 */ 1411 1412 #ifdef __cplusplus 1413 } 1414 #endif 1415 1416 #endif /* STM32F4xx_LL_FMC_H */ 1417
