Home
last modified time | relevance | path

Searched refs:regs (Results 1 – 25 of 53) sorted by relevance

123

/hal_microchip-latest/mec5/drivers/
Dmec_vci.c41 uint32_t mec_hal_vci_in_pin_states(struct mec_vci_regs *regs) in mec_hal_vci_in_pin_states() argument
43 if (!regs) { in mec_hal_vci_in_pin_states()
47 return (regs->CONFIG & 0x3037fu); in mec_hal_vci_in_pin_states()
50 uint8_t mec_hal_vci_out_get(struct mec_vci_regs *regs) in mec_hal_vci_out_get() argument
52 if (!regs) { in mec_hal_vci_out_get()
56 return (uint8_t)((regs->CONFIG >> MEC_VCI_CONFIG_VCI_OUT_Pos) & MEC_BIT(0)); in mec_hal_vci_out_get()
59 uint8_t mec_hal_vci_ovrd_in_get(struct mec_vci_regs *regs) in mec_hal_vci_ovrd_in_get() argument
61 if (!regs) { in mec_hal_vci_ovrd_in_get()
65 return (uint8_t)((regs->CONFIG >> MEC_VCI_CONFIG_VCI_OVRD_IN_Pos) & MEC_BIT(0)); in mec_hal_vci_ovrd_in_get()
69 int mec_hal_vci_in_filter_enable(struct mec_vci_regs *regs, uint8_t enable) in mec_hal_vci_in_filter_enable() argument
[all …]
Dmec_i3c_pvt.c23 uint32_t _i3c_intr_sts_get(struct mec_i3c_host_regs *regs) in _i3c_intr_sts_get() argument
25 return regs->INTR_STS; in _i3c_intr_sts_get()
33 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_clear() argument
35 regs->INTR_STS = mask; in _i3c_intr_sts_clear()
43 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_enable() argument
45 regs->INTR_EN = mask; in _i3c_intr_sts_enable()
53 void _i3c_intr_IBI_enable(struct mec_i3c_host_regs *regs) in _i3c_intr_IBI_enable() argument
55 regs->INTR_EN |= sbit_IBI_THLD_STS; in _i3c_intr_IBI_enable()
57 regs->INTR_SIG_EN |= sbit_IBI_THLD_STS; in _i3c_intr_IBI_enable()
65 void _i3c_intr_IBI_disable(struct mec_i3c_host_regs *regs) in _i3c_intr_IBI_disable() argument
[all …]
Dmec_peci.c29 static void peci_reset(struct mec_peci_regs *regs) in peci_reset() argument
31 regs->CTRL = (MEC_BIT(MEC_PECI_CTRL_RST_Pos) | MEC_BIT(MEC_PECI_CTRL_FRST_Pos) in peci_reset()
33 regs->IEN1 = 0u; in peci_reset()
34 regs->IEN2 = 0u; in peci_reset()
35 regs->STATUS1 = UINT8_MAX; in peci_reset()
36 regs->STATUS1 = UINT8_MAX; in peci_reset()
37 regs->CTRL = MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos); in peci_reset()
46 static void peci_intr_en(struct mec_peci_regs *regs, uint16_t ien_bitmap) in peci_intr_en() argument
52 regs->IEN1 |= (uint8_t)(ien_bitmap & 0xffu); in peci_intr_en()
53 regs->IEN2 |= (uint8_t)((ien_bitmap >> 8) & 0xffu); in peci_intr_en()
[all …]
Dmec_bbled.c83 static uint8_t bbled_get_pwm_size(struct mec_bbled_regs *regs) in bbled_get_pwm_size() argument
85 return (uint8_t)((regs->CONFIG & MEC_BBLED_CONFIG_PWM_SZ_Msk) >> MEC_BBLED_CONFIG_PWM_SZ_Pos); in bbled_get_pwm_size()
88 static void bbled_set_pwm_size(struct mec_bbled_regs *regs, uint8_t pwm_width) in bbled_set_pwm_size() argument
90 regs->CONFIG = (regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_PWM_SZ_Msk) | in bbled_set_pwm_size()
94 static void bbled_set_clk_src(struct mec_bbled_regs *regs, uint8_t use_sys_clk) in bbled_set_clk_src() argument
97 regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos); in bbled_set_clk_src()
99 regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos); in bbled_set_clk_src()
103 static void bbled_set_wdt_reload(struct mec_bbled_regs *regs, uint32_t bbcfg) in bbled_set_wdt_reload() argument
107 regs->CONFIG = ((regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_WDTRLD_Msk) | in bbled_set_wdt_reload()
111 static void bbled_set_mode(struct mec_bbled_regs *regs, uint8_t mode) in bbled_set_mode() argument
[all …]
Dmec_i3c.c58 struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base; in MEC_HAL_I3C_Controller_Clk_I2C_Init() local
72 _i2c_fmp_timing_set(regs, core_clk_freq_ns); in MEC_HAL_I3C_Controller_Clk_I2C_Init()
74 _i2c_fm_timing_set(regs, core_clk_freq_ns); in MEC_HAL_I3C_Controller_Clk_I2C_Init()
76 _i2c_target_present_set(regs); in MEC_HAL_I3C_Controller_Clk_I2C_Init()
113 struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base; in MEC_HAL_I3C_Controller_Clk_Cfg() local
121 _i3c_push_pull_timing_set(regs, core_clk_freq_ns, i3c_freq_ns); in MEC_HAL_I3C_Controller_Clk_Cfg()
124 _i3c_open_drain_timing_set(regs, core_clk_freq_ns, i3c_freq_ns); in MEC_HAL_I3C_Controller_Clk_Cfg()
126 _i3c_sda_hld_timing_set(regs, SDA_TX_HOLD_4); in MEC_HAL_I3C_Controller_Clk_Cfg()
127 _i3c_read_term_bit_low_count_set(regs, RD_TERM_BIT_LCNT_4); in MEC_HAL_I3C_Controller_Clk_Cfg()
138 struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base; in MEC_HAL_I3C_Target_Init() local
[all …]
Dmec_btimer_api.h42 int mec_hal_btimer_has_counter32(struct mec_btmr_regs *regs);
45 int mec_hal_btimer_init(struct mec_btmr_regs *regs, uint32_t freq_div,
50 int mec_hal_btimer_reset(struct mec_btmr_regs *regs, uint32_t flags);
52 int mec_hal_btimer_girq_ctrl(struct mec_btmr_regs *regs, uint8_t enable);
53 int mec_hal_btimer_girq_status_clr(struct mec_btmr_regs *regs);
55 uint32_t mec_hal_btimer_freq(struct mec_btmr_regs *regs);
57 void mec_hal_btimer_pre_and_reload(struct mec_btmr_regs *regs,
63 void mec_hal_btimer_start_load(struct mec_btmr_regs *regs, uint32_t initial_count,
65 void mec_hal_btimer_auto_restart(struct mec_btmr_regs *regs, uint8_t enable);
66 bool mec_hal_btimer_is_auto_restart(struct mec_btmr_regs *regs);
[all …]
Dmec_wdt.c38 int mec_hal_wdt_init(struct mec_wdt_regs *regs, uint16_t n32k_ticks, uint32_t flags) in mec_hal_wdt_init() argument
42 if ((uintptr_t)regs != (uintptr_t)MEC_WDT0_BASE) { in mec_hal_wdt_init()
46 regs->CTRL = ctrl; in mec_hal_wdt_init()
47 regs->IEN = 0u; in mec_hal_wdt_init()
48 regs->STATUS = UINT32_MAX; in mec_hal_wdt_init()
53 regs->LOAD = n32k_ticks; in mec_hal_wdt_init()
69 regs->IEN |= MEC_BIT(MEC_WDT_IEN_INTREN_Pos); in mec_hal_wdt_init()
73 regs->CTRL = ctrl; in mec_hal_wdt_init()
78 bool mec_hal_wdt_is_enabled(struct mec_wdt_regs *regs) in mec_hal_wdt_is_enabled() argument
80 if (regs->CTRL & MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos)) { in mec_hal_wdt_is_enabled()
[all …]
Dmec_btimer.c59 static inline uint32_t btimer_fast_idx(struct mec_btmr_regs *regs) in btimer_fast_idx() argument
61 return (((uint32_t)regs >> 5) & 0x7u); in btimer_fast_idx()
98 int mec_hal_btimer_init(struct mec_btmr_regs *regs, uint32_t freq_div, in mec_hal_btimer_init() argument
101 const struct mec_btimer_info *info = find_btimer_info((uintptr_t)regs); in mec_hal_btimer_init()
110 regs->CTRL = MEC_BIT(MEC_BTMR_CTRL_RESET_Pos); in mec_hal_btimer_init()
111 regs->CTRL = ((freq_div - 1u) & MEC5_BTMR_PRESCALE_MSK0) << MEC_BTMR_CTRL_PRESCALE_Pos; in mec_hal_btimer_init()
112 regs->PRELOAD = count; in mec_hal_btimer_init()
113 regs->COUNT = count; in mec_hal_btimer_init()
117 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos); in mec_hal_btimer_init()
120 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_RESTART_Pos); in mec_hal_btimer_init()
[all …]
Dmec_acpi_ec.c99 int mec_hal_acpi_ec_init(struct mec_acpi_ec_regs *regs, uint32_t flags) in mec_hal_acpi_ec_init() argument
101 const struct mec_acpi_ec_info *info = find_acpi_ec_info((uintptr_t)regs); in mec_hal_acpi_ec_init()
109 mec_hal_acpi_ec_girq_dis(regs, MEC_ACPI_EC_IBF_IRQ | MEC_ACPI_EC_OBE_IRQ); in mec_hal_acpi_ec_init()
114 regs->AEC_H2E_DATA; in mec_hal_acpi_ec_init()
117 mec_hal_acpi_ec_girq_clr(regs, MEC_ACPI_EC_IBF_IRQ | MEC_ACPI_EC_OBE_IRQ); in mec_hal_acpi_ec_init()
120 regs->AEC_BYTE_CTRL |= MEC_BIT(MEC_ACPI_EC_AEC_BYTE_CTRL_FOUR_BYTE_MODE_Pos); in mec_hal_acpi_ec_init()
122 regs->AEC_BYTE_CTRL &= (uint8_t)~MEC_BIT(MEC_ACPI_EC_AEC_BYTE_CTRL_FOUR_BYTE_MODE_Pos); in mec_hal_acpi_ec_init()
127 regs->AEC_STATUS |= MEC_BIT(MEC_ACPI_EC_AEC_STATUS_UD0A_Pos); in mec_hal_acpi_ec_init()
129 regs->AEC_STATUS &= (uint8_t)~MEC_BIT(MEC_ACPI_EC_AEC_STATUS_UD0A_Pos); in mec_hal_acpi_ec_init()
135 regs->AEC_STATUS |= MEC_BIT(MEC_ACPI_EC_AEC_STATUS_UD1A_Pos); in mec_hal_acpi_ec_init()
[all …]
Dmec_i3c_pvt.h578 uint32_t _i3c_intr_sts_get(struct mec_i3c_host_regs *regs);
579 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask);
580 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
581 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
582 void _i3c_intr_IBI_enable(struct mec_i3c_host_regs *regs);
583 void _i3c_intr_IBI_disable(struct mec_i3c_host_regs *regs);
585 void _i3c_resp_buf_threshold_set(struct mec_i3c_host_regs *regs, uint8_t threshold);
586 void _i3c_cmd_queue_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
587 void _i3c_tx_fifo_empty_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
588 void _i3c_rx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
[all …]
Dmec_pwm.c73 static void pwm_disable(struct mec_pwm_regs *regs) in pwm_disable() argument
75 regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_PWM_CONFIG_ENABLE_Pos); in pwm_disable()
78 static void pwm_enable(struct mec_pwm_regs *regs) in pwm_enable() argument
80 regs->CONFIG |= MEC_BIT(MEC_PWM_CONFIG_ENABLE_Pos); in pwm_enable()
84 static void pwm_off(struct mec_pwm_regs *regs) in pwm_off() argument
86 regs->CNT_ON = 0u; in pwm_off()
87 regs->CNT_OFF = 1u; in pwm_off()
91 static void pwm_on(struct mec_pwm_regs *regs) in pwm_on() argument
93 regs->CNT_OFF = 0u; in pwm_on()
94 regs->CNT_ON = 1u; in pwm_on()
[all …]
Dmec_eeprom.c28 int mec_hal_eeprom_init(struct mec_eeprom_ctrl_regs *regs, uint32_t flags, uint32_t password) in mec_hal_eeprom_init() argument
30 if ((uintptr_t)regs != (uintptr_t)MEC_EEPROM_CTRL0_BASE) { in mec_hal_eeprom_init()
40 regs->MODE |= MEC_BIT(MEC_EEPROM_CTRL_MODE_SRST_Pos); in mec_hal_eeprom_init()
42 regs->MODE = 0; in mec_hal_eeprom_init()
43 regs->INTR_EN = 0; in mec_hal_eeprom_init()
44 regs->STATUS = UINT32_MAX; in mec_hal_eeprom_init()
48 regs->PSWD = password; in mec_hal_eeprom_init()
52 regs->LOCK |= MEC_BIT(MEC_EEPROM_CTRL_LOCK_LOCK_Pos); in mec_hal_eeprom_init()
56 regs->LOCK |= MEC_BIT(MEC_EEPROM_CTRL_LOCK_JTAG_LOCK_Pos); in mec_hal_eeprom_init()
60 regs->INTR_EN |= MEC_BIT(MEC_EEPROM_CTRL_INTR_EN_XFR_DONE_Pos); in mec_hal_eeprom_init()
[all …]
Dmec_rtimer_api.h41 int mec_hal_rtimer_init(struct mec_rtmr_regs *regs, uint32_t rtmr_config, uint32_t preload);
43 void mec_hal_rtimer_restart(struct mec_rtmr_regs *regs, uint32_t new_count, uint8_t restart);
45 uint32_t mec_hal_rtimer_status(struct mec_rtmr_regs *regs);
46 void mec_hal_rtimer_status_clear(struct mec_rtmr_regs *regs, uint32_t status);
47 void mec_hal_rtimer_status_clear_all(struct mec_rtmr_regs *regs);
49 void mec_hal_rtimer_intr_ctrl(struct mec_rtmr_regs *regs, uint8_t enable);
51 static inline void mec_hal_rtimer_auto_reload(struct mec_rtmr_regs *regs, uint8_t enable) in mec_hal_rtimer_auto_reload() argument
54 regs->CTRL |= MEC_BIT(MEC_RTMR_CTRL_AUTO_RELOAD_Pos); in mec_hal_rtimer_auto_reload()
56 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_RTMR_CTRL_AUTO_RELOAD_Pos); in mec_hal_rtimer_auto_reload()
60 static inline void mec_hal_rtimer_stop(struct mec_rtmr_regs *regs) in mec_hal_rtimer_stop() argument
[all …]
Dmec_kscan.c36 static void kscan_default(struct mec_kscan_regs *regs) in kscan_default() argument
38 regs->KSI_INT_EN = 0; in kscan_default()
39 regs->KSO_SEL = MEC_KSCAN_KSO_SEL_DLFT; in kscan_default()
40 regs->EXT_CTRL = 0; in kscan_default()
41 regs->KSI_STS = 0xffu; in kscan_default()
53 int mec_hal_kscan_init(struct mec_kscan_regs *regs, uint32_t flags, uint8_t ksi_in_intr_mask) in mec_hal_kscan_init() argument
56 if ((uintptr_t)regs != (uintptr_t)MEC_KSCAN0_BASE) { in mec_hal_kscan_init()
65 kscan_default(regs); in mec_hal_kscan_init()
71 regs->EXT_CTRL |= MEC_BIT(MEC_KSCAN_EXT_CTRL_PREDRIVE_Pos); in mec_hal_kscan_init()
78 regs->KSO_SEL |= MEC_BIT(MEC_KSCAN_KSO_SEL_KSO_INVERT_Pos); in mec_hal_kscan_init()
[all …]
Dmec_bclink.c78 int mec_hal_bcl_soft_reset(struct mec_bcl_regs *regs, uint8_t enable) in mec_hal_bcl_soft_reset() argument
81 if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) { in mec_hal_bcl_soft_reset()
87 regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_soft_reset()
89 regs->STATUS = (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_soft_reset()
95 int mec_hal_bcl_get_freq(struct mec_bcl_regs *regs, uint32_t *freq_hz) in mec_hal_bcl_get_freq() argument
98 if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) { in mec_hal_bcl_get_freq()
106 uint32_t fdiv = (regs->CLKSEL & 0xffu); in mec_hal_bcl_get_freq()
113 bool mec_hal_bcl_is_busy(struct mec_bcl_regs *regs) in mec_hal_bcl_is_busy() argument
116 if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) { in mec_hal_bcl_is_busy()
121 if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BUSY_Pos)) { in mec_hal_bcl_is_busy()
[all …]
Dmec_adc.c39 int mec_hal_adc_init(struct mec_adc_regs *regs, struct mec_adc_config *cfg) in mec_hal_adc_init() argument
45 if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) { in mec_hal_adc_init()
53 regs->CTRL = 0; in mec_hal_adc_init()
59 regs->CTRL = MEC_BIT(MEC_ADC_CTRL_SRST_Pos); in mec_hal_adc_init()
61 if (!(regs->CTRL & MEC_BIT(MEC_ADC_CTRL_SRST_Pos))) { in mec_hal_adc_init()
65 regs->CTRL = 0; in mec_hal_adc_init()
69 regs->CTRL |= MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos); in mec_hal_adc_init()
71 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos); in mec_hal_adc_init()
79 regs->CONFIG = (regs->CONFIG & (uint32_t)~(MEC_ADC_CONFIG_CLTM_Msk in mec_hal_adc_init()
85 regs->SAR_CTRL = (regs->SAR_CTRL & (uint32_t)~(MEC_ADC_SAR_CTRL_WARMUPDLY_Msk)) in mec_hal_adc_init()
[all …]
Dmec_bdp.c41 int mec_hal_bdp_init(struct mec_bdp_regs *regs, uint32_t cfg_flags) in mec_hal_bdp_init() argument
45 if (!regs) { in mec_hal_bdp_init()
52 regs->ACTV80 = 0; in mec_hal_bdp_init()
53 regs->ACTV80A = 0; in mec_hal_bdp_init()
56 regs->CONFIG = MEC_BIT(MEC_BDP_CFG_REG_SRESET_POS); in mec_hal_bdp_init()
60 regs->CONFIG = (regs->CONFIG & (uint32_t)~(MEC_BDP_CFG_REG_FIFO_THRH_MSK)) in mec_hal_bdp_init()
65 regs->BL80A = in mec_hal_bdp_init()
71 regs->IEN |= MEC_BIT(MEC_BDP_IEN_REG_THRH_POS); in mec_hal_bdp_init()
77 regs->ACTV80A |= MEC_BIT(MEC_BDP_ACTV_REG_EN_POS); in mec_hal_bdp_init()
82 regs->ACTV80 |= MEC_BIT(MEC_BDP_ACTV_REG_EN_POS); in mec_hal_bdp_init()
[all …]
Dmec_kscan_api.h72 int mec_hal_kscan_init(struct mec_kscan_regs *regs, uint32_t flags, uint8_t ksi_in_intr_mask);
74 int mec_hal_kscan_enable(struct mec_kscan_regs *regs, uint8_t enable);
75 bool mec_hal_kscan_is_enabled(struct mec_kscan_regs *regs);
77 int mec_hal_kscan_kso_pre_drive_enable(struct mec_kscan_regs *regs, uint8_t enable);
79 int mec_hal_kscan_girq_en(struct mec_kscan_regs *regs);
80 int mec_hal_kscan_girq_dis(struct mec_kscan_regs *regs);
81 int mec_hal_kscan_girq_clr(struct mec_kscan_regs *regs);
82 uint32_t mec_hal_kscan_girq_result(struct mec_kscan_regs *regs);
90 static inline void mec_hal_kscan_kso_drive_all(struct mec_kscan_regs *regs) in mec_hal_kscan_kso_drive_all() argument
92 regs->KSO_SEL = (regs->KSO_SEL & (uint8_t)~MEC_BIT(MEC_KSCAN_KSO_SEL_KSCAN_DIS_Pos)) in mec_hal_kscan_kso_drive_all()
[all …]
Dmec_vci_api.h48 uint32_t mec_hal_vci_in_pin_states(struct mec_vci_regs *regs);
51 int mec_hal_vci_in_filter_enable(struct mec_vci_regs *regs, uint8_t enable);
56 int mec_hal_vci_sw_vci_out_set(struct mec_vci_regs *regs, uint8_t pin_state);
59 int mec_hal_vci_sw_vci_out_enable(struct mec_vci_regs *regs, uint8_t enable);
61 uint8_t mec_hal_vci_out_get(struct mec_vci_regs *regs);
62 uint8_t mec_hal_vci_ovrd_in_get(struct mec_vci_regs *regs);
65 uint32_t mec_hal_vci_in_latched_get(struct mec_vci_regs *regs);
67 int mec_hal_vci_in_latch_enable(struct mec_vci_regs *regs, uint32_t latch_bitmap);
68 int mec_hal_vci_in_latch_disable(struct mec_vci_regs *regs, uint32_t latch_bitmap);
69 uint32_t mec_hal_vci_in_latch_enable_get(struct mec_vci_regs *regs);
[all …]
Dmec_emi.c107 int mec_hal_emi_init(struct mec_emi_regs *regs, uint32_t flags) in mec_hal_emi_init() argument
109 const struct mec_emi_info *info = find_emi_info((uintptr_t)regs); in mec_hal_emi_init()
153 int mec_hal_emi_mem_region_config(struct mec_emi_regs *regs, uint8_t region, in mec_hal_emi_mem_region_config() argument
156 const struct mec_emi_info *info = find_emi_info((uintptr_t)regs); in mec_hal_emi_mem_region_config()
173 regs->MR0L = 0u; in mec_hal_emi_mem_region_config()
174 regs->MR0B = mbase; in mec_hal_emi_mem_region_config()
175 regs->MR0L = rwszs; in mec_hal_emi_mem_region_config()
177 regs->MR1L = 0u; in mec_hal_emi_mem_region_config()
178 regs->MR1B = mbase; in mec_hal_emi_mem_region_config()
179 regs->MR1L = rwszs; in mec_hal_emi_mem_region_config()
[all …]
Dmec_htimer.c25 int mec_hal_htimer_init(struct mec_htmr_regs *regs, struct mec_htimer_context *ctx, in mec_hal_htimer_init() argument
35 switch ((uintptr_t)regs) { in mec_hal_htimer_init()
37 ctx->regs = regs; in mec_hal_htimer_init()
42 ctx->regs = regs; in mec_hal_htimer_init()
52 regs->PRELOAD = 0; in mec_hal_htimer_init()
53 regs->CTRL = 0; in mec_hal_htimer_init()
58 regs->CTRL |= MEC_BIT(MEC_HTMR_CTRL_RES_Pos); in mec_hal_htimer_init()
72 regs->PRELOAD = ctx->preload; in mec_hal_htimer_init()
96 void mec_hal_htimer_stop(struct mec_htmr_regs *regs) in mec_hal_htimer_stop() argument
98 regs->PRELOAD = 0; in mec_hal_htimer_stop()
[all …]
Dmec_tach.c38 static struct mec_tach_info const *tach_get_info(struct mec_tach_regs *regs) in tach_get_info() argument
43 if (tach_instances[i].base_addr == (uintptr_t)regs) { in tach_get_info()
51 int mec_hal_tach_init(struct mec_tach_regs *regs, uint32_t limits, uint32_t flags) in mec_hal_tach_init() argument
53 const struct mec_tach_info *info = tach_get_info(regs); in mec_hal_tach_init()
65 regs->CTRL = 0u; in mec_hal_tach_init()
66 regs->STATUS = UINT32_MAX; in mec_hal_tach_init()
73 regs->LIMIT_LO = (uint16_t)(limits & 0xffffu); in mec_hal_tach_init()
74 regs->LIMIT_HI = (uint16_t)(limits >> 16); in mec_hal_tach_init()
114 regs->CTRL = ctrl; in mec_hal_tach_init()
119 void mec_hal_tach_enable(struct mec_tach_regs *regs, uint8_t enable) in mec_hal_tach_enable() argument
[all …]
Dmec_acpi_ec_api.h52 int mec_hal_acpi_ec_init(struct mec_acpi_ec_regs *regs, uint32_t flags);
53 int mec_hal_acpi_ec_is_enabled(struct mec_acpi_ec_regs *regs);
54 int mec_hal_acpi_ec_is_4byte_mode(struct mec_acpi_ec_regs *regs);
56 uint8_t mec_hal_acpi_ec_status(struct mec_acpi_ec_regs *regs);
57 void mec_hal_acpi_ec_status_wr(struct mec_acpi_ec_regs *regs, uint8_t val);
58 void mec_hal_acpi_ec_status_set(struct mec_acpi_ec_regs *regs, uint8_t val);
59 void mec_hal_acpi_ec_status_mask(struct mec_acpi_ec_regs *regs, uint8_t val, uint8_t msk);
60 uint8_t mec_hal_acpi_ec_status_obf(struct mec_acpi_ec_regs *regs);
61 uint8_t mec_hal_acpi_ec_status_ibf(struct mec_acpi_ec_regs *regs);
63 uint32_t mec_hal_acpi_ec_host_to_ec_data_rd32(struct mec_acpi_ec_regs *regs);
[all …]
Dmec_bbled_api.h80 bool mec_hal_bbled_is_valid(struct mec_bbled_regs *regs);
82 bool mec_hal_bbled_is_off(struct mec_bbled_regs *regs);
84 int mec_hal_bbled_init(struct mec_bbled_regs *regs, uint32_t bbled_config);
86 uint32_t mec_hal_bbled_clk_freq(struct mec_bbled_regs *regs);
88 int mec_hal_bbled_mode(struct mec_bbled_regs *regs, uint8_t mode);
89 uint8_t mec_hal_bbled_mode_get(struct mec_bbled_regs *regs);
96 int mec_hal_bbled_breathe_pwm_width(struct mec_bbled_regs *regs, uint8_t pwm_width);
97 uint8_t mec_hal_bbled_breathe_pwm_width_get(struct mec_bbled_regs *regs);
104 int mec_hal_bbled_blink_clk_sel(struct mec_bbled_regs *regs, uint8_t blink_clk_sel);
105 uint8_t mec_hal_bbled_blink_clk_sel_get(struct mec_bbled_regs *regs);
[all …]
Dmec_espi_taf.c59 static inline bool taf_regs_valid(struct mec_espi_taf_regs *regs) in taf_regs_valid() argument
61 if (((uintptr_t)regs != (uintptr_t)MEC_ESPI_TAF_BASE)) { in taf_regs_valid()
67 static inline bool taf_regs_valid(struct mec_espi_taf_regs *regs) { return true; } in taf_regs_valid() argument
83 static bool pr_is_dirty(struct mec_espi_taf_regs *regs, uint8_t pridx) in pr_is_dirty() argument
85 if (regs->PR_DIRTY & MEC_BIT(pridx)) { in pr_is_dirty()
91 static void taf_disable_clear_intr(struct mec_espi_taf_regs *regs) in taf_disable_clear_intr() argument
94 regs->FC_MISC = 0u; in taf_disable_clear_intr()
95 regs->ECP_IEN = 0; in taf_disable_clear_intr()
96 regs->MON_IEN = 0; in taf_disable_clear_intr()
100 regs->ECP_STS = UINT32_MAX; in taf_disable_clear_intr()
[all …]

123