58     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Controller_Clk_I2C_Init()  local
72         _i2c_fmp_timing_set(regs, core_clk_freq_ns);  in MEC_HAL_I3C_Controller_Clk_I2C_Init()
74         _i2c_fm_timing_set(regs, core_clk_freq_ns);  in MEC_HAL_I3C_Controller_Clk_I2C_Init()
76         _i2c_target_present_set(regs);  in MEC_HAL_I3C_Controller_Clk_I2C_Init()
113     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Controller_Clk_Cfg()  local
121     _i3c_push_pull_timing_set(regs, core_clk_freq_ns, i3c_freq_ns);  in MEC_HAL_I3C_Controller_Clk_Cfg()
124     _i3c_open_drain_timing_set(regs, core_clk_freq_ns, i3c_freq_ns);  in MEC_HAL_I3C_Controller_Clk_Cfg()
126     _i3c_sda_hld_timing_set(regs, SDA_TX_HOLD_4);  in MEC_HAL_I3C_Controller_Clk_Cfg()
127     _i3c_read_term_bit_low_count_set(regs, RD_TERM_BIT_LCNT_4);  in MEC_HAL_I3C_Controller_Clk_Cfg()
138     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Target_Init()  local
153         _i3c_bus_available_timing_set(regs, core_clk_freq_ns);  in MEC_HAL_I3C_Target_Init()
156         _i3c_bus_idle_timing_set(regs, core_clk_freq_ns);  in MEC_HAL_I3C_Target_Init()
158         _i3c_bus_free_timing_set(regs, core_clk_freq_ns);  in MEC_HAL_I3C_Target_Init()
160         _i3c_tgt_MRL_get(regs, max_rd_len);  in MEC_HAL_I3C_Target_Init()
161         _i3c_tgt_MWL_get(regs, max_wr_len);  in MEC_HAL_I3C_Target_Init()
163         _i3c_sda_hld_switch_delay_timing_set(regs, SDA_OD_PP_SWITCH_DLY_0,  in MEC_HAL_I3C_Target_Init()
166         _i3c_scl_low_mst_tout_set(regs, 0x003567E0);  in MEC_HAL_I3C_Target_Init()
168         _i3c_tgt_max_speed_update(regs, TGT_MAX_RD_DATA_SPEED, TGT_MAX_WR_DATA_SPEED);  in MEC_HAL_I3C_Target_Init()
170         _i3c_tgt_clk_to_data_turn_update(regs, TGT_CLK_TO_DATA_TURN);  in MEC_HAL_I3C_Target_Init()
187     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Target_MRL_MWL_update()  local
189     if (_i3c_tgt_MRL_updated(regs)) {  in MEC_HAL_I3C_Target_MRL_MWL_update()
190         _i3c_tgt_MRL_get(regs, max_rd_len);  in MEC_HAL_I3C_Target_MRL_MWL_update()
193     if (_i3c_tgt_MWL_updated(regs)) {  in MEC_HAL_I3C_Target_MRL_MWL_update()
194         _i3c_tgt_MWL_get(regs, max_wr_len);  in MEC_HAL_I3C_Target_MRL_MWL_update()
206     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Target_MRL_MWL_set()  local
208     _i3c_tgt_MRL_MWL_set(regs, max_rd_len, max_wr_len);  in MEC_HAL_I3C_Target_MRL_MWL_set()
218     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Target_Interrupts_Init()  local
225     _i3c_intr_sts_clear(regs, mask);  in MEC_HAL_I3C_Target_Interrupts_Init()
234     _i3c_intr_sts_enable(regs, mask);  in MEC_HAL_I3C_Target_Interrupts_Init()
237     _i3c_intr_sgnl_enable(regs, mask);  in MEC_HAL_I3C_Target_Interrupts_Init()
251     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Controller_Interrupts_Init()  local
259     _i3c_intr_sts_clear(regs, mask);  in MEC_HAL_I3C_Controller_Interrupts_Init()
267     _i3c_intr_sts_enable(regs, mask);  in MEC_HAL_I3C_Controller_Interrupts_Init()
270     _i3c_intr_sgnl_enable(regs, mask);  in MEC_HAL_I3C_Controller_Interrupts_Init()
284     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Thresholds_Init()  local
287     _i3c_cmd_queue_threshold_set(regs, 0x00);  in MEC_HAL_I3C_Thresholds_Init()
290     _i3c_resp_queue_threshold_set(regs, 0x00);  in MEC_HAL_I3C_Thresholds_Init()
293     _i3c_ibi_data_threshold_set(regs, 10);  in MEC_HAL_I3C_Thresholds_Init()
296     _i3c_ibi_status_threshold_set(regs, 0x00);  in MEC_HAL_I3C_Thresholds_Init()
299     _i3c_tx_buf_threshold_set(regs, DATA_BUF_THLD_TX_FIFO_EMPTY_1);  in MEC_HAL_I3C_Thresholds_Init()
302     _i3c_rx_buf_threshold_set(regs, DATA_BUF_THLD_RX_FIFO_1);  in MEC_HAL_I3C_Thresholds_Init()
305     _i3c_tx_start_threshold_set(regs, DATA_BUF_THLD_TX_FIFO_START_1);  in MEC_HAL_I3C_Thresholds_Init()
308     _i3c_rx_start_threshold_set(regs, DATA_BUF_THLD_RX_FIFO_START_1);  in MEC_HAL_I3C_Thresholds_Init()
311     _i3c_notify_sir_reject(regs, false);  in MEC_HAL_I3C_Thresholds_Init()
314     _i3c_notify_mr_reject(regs, false);  in MEC_HAL_I3C_Thresholds_Init()
317     _i3c_notify_hj_reject(regs, false);  in MEC_HAL_I3C_Thresholds_Init()
328     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Thresholds_Response_buf_set()  local
330     _i3c_resp_queue_threshold_set(regs, threshold);  in MEC_HAL_I3C_Thresholds_Response_buf_set()
340     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Host_Config()  local
342     _i3c_host_dma_tx_burst_length_set(regs, HOST_CFG_DMA_TX_BURST_LENGTH_4);  in MEC_HAL_I3C_Host_Config()
344     _i3c_host_dma_rx_burst_length_set(regs, HOST_CFG_DMA_RX_BURST_LENGTH_4);  in MEC_HAL_I3C_Host_Config()
346     _i3c_host_port_set(regs, HOST_CFG_PORT_SEL_I3C1);  in MEC_HAL_I3C_Host_Config()
348     _i3c_host_stuck_sda_config(regs, HOST_CFG_STUCK_SDA_DISABLE, 0xFFFFU);  in MEC_HAL_I3C_Host_Config()
350     _i3c_host_tx_dma_tout_config(regs, HOST_CFG_TX_DMA_TOUT_DISABLE, 0xFFFFU);  in MEC_HAL_I3C_Host_Config()
352     _i3c_host_rx_dma_tout_config(regs, HOST_CFG_RX_DMA_TOUT_DISABLE, 0xFFFFU);  in MEC_HAL_I3C_Host_Config()
362     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Sec_Host_Config()  local
364     _i3c_sec_host_dma_tx_burst_length_set(regs, SEC_HOST_CFG_DMA_TX_BURST_LENGTH_4);  in MEC_HAL_I3C_Sec_Host_Config()
366     _i3c_sec_host_dma_rx_burst_length_set(regs, SEC_HOST_CFG_DMA_RX_BURST_LENGTH_4);  in MEC_HAL_I3C_Sec_Host_Config()
368     _i3c_sec_host_port_set(regs, SEC_HOST_CFG_PORT_SEL_I3C0);  in MEC_HAL_I3C_Sec_Host_Config()
370     _i3c_sec_host_stuck_sda_scl_config(regs, SEC_HOST_CFG_STUCK_SDA_SCL_DISABLE, 0xFFFFU, 0xFFFFU);  in MEC_HAL_I3C_Sec_Host_Config()
372     _i3c_sec_host_tx_dma_tout_config(regs, HOST_CFG_TX_DMA_TOUT_DISABLE, 0xFFFFU);  in MEC_HAL_I3C_Sec_Host_Config()
374     _i3c_sec_host_rx_dma_tout_config(regs, HOST_CFG_RX_DMA_TOUT_DISABLE, 0xFFFFU);  in MEC_HAL_I3C_Sec_Host_Config()
384     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Soft_Reset()  local
386     _i3c_soft_reset(regs);  in MEC_HAL_I3C_Soft_Reset()
398     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DAT_info_get()  local
400     _i3c_dev_addr_table_ptr_get(regs, start_addr, depth);  in MEC_HAL_I3C_DAT_info_get()
412     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DCT_info_get()  local
414     _i3c_dev_char_table_ptr_get(regs, start_addr, depth);  in MEC_HAL_I3C_DCT_info_get()
425     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Is_Current_Role_Primary()  local
427     if (_i3c_dev_role_config_get(regs) != MEC_I3C_ROLE_CFG_PRIM_CTRLR) {  in MEC_HAL_I3C_Is_Current_Role_Primary()
442     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Is_Current_Role_Master()  local
444     if (((_i3c_dev_role_config_get(regs) == MEC_I3C_ROLE_CFG_SEC_CTRLR) &&  in MEC_HAL_I3C_Is_Current_Role_Master()
445         (_i3c_dev_operation_mode_get(regs) != 0)) ||  in MEC_HAL_I3C_Is_Current_Role_Master()
446         _i3c_dev_role_config_get(regs) == MEC_I3C_ROLE_CFG_TGT) {  in MEC_HAL_I3C_Is_Current_Role_Master()
460     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Is_Current_Role_BusMaster()  local
462     if ((_i3c_dev_role_config_get(regs) == MEC_I3C_ROLE_CFG_SEC_CTRLR) &&  in MEC_HAL_I3C_Is_Current_Role_BusMaster()
463         (_i3c_dev_controller_role_get(regs) != 1U)) {  in MEC_HAL_I3C_Is_Current_Role_BusMaster()
482     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_queue_depths_get()  local
484     *tx_depth = _i3c_tx_fifo_depth_get(regs);  in MEC_HAL_I3C_queue_depths_get()
485     *rx_depth = _i3c_rx_fifo_depth_get(regs);  in MEC_HAL_I3C_queue_depths_get()
486     *cmd_depth = _i3c_cmd_fifo_depth_get(regs);  in MEC_HAL_I3C_queue_depths_get()
487     *resp_depth = _i3c_resp_fifo_depth_get(regs);  in MEC_HAL_I3C_queue_depths_get()
488     *ibi_depth = _i3c_ibi_fifo_depth_get(regs);  in MEC_HAL_I3C_queue_depths_get()
501     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Enable()  local
509         _i3c_static_addr_set(regs, address);  in MEC_HAL_I3C_Enable()
511         _i3c_dynamic_addr_set(regs, address);  in MEC_HAL_I3C_Enable()
517             _i3c_tgt_hot_join_disable((struct mec_i3c_sec_regs *)regs);  in MEC_HAL_I3C_Enable()
521             _i3c_hot_join_disable(regs);  in MEC_HAL_I3C_Enable()
528             _i3c_intr_IBI_enable(regs);  in MEC_HAL_I3C_Enable()
535         _i3c_operation_mode_set(regs, mode);  in MEC_HAL_I3C_Enable()
542         _i3c_enable(regs, mode, enable_dma);  in MEC_HAL_I3C_Enable()
552         _i3c_disable(regs);  in MEC_HAL_I3C_Enable()
567     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DCT_read()  local
569     _i3c_DCT_read(regs, DCT_start, (uint8_t)DCT_idx, info);  in MEC_HAL_I3C_DCT_read()
582     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_DEFTGTS_DAT_write()  local
597         _i3c_DAT_write(regs, DAT_start, i, val);  in MEC_HAL_I3C_TGT_DEFTGTS_DAT_write()
613     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_SDCT_read()  local
615     _i3c_SDCT_read(regs, DCT_start, (uint8_t)idx, info);  in MEC_HAL_I3C_SDCT_read()
629     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DAT_DynamicAddr_write()  local
634     _i3c_DAT_write(regs, DAT_start, (uint8_t)DAT_idx, val);  in MEC_HAL_I3C_DAT_DynamicAddr_write()
648     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DAT_DynamicAddrAssign_write()  local
658     _i3c_DAT_write(regs, DAT_start, (uint8_t)DAT_idx, val);  in MEC_HAL_I3C_DAT_DynamicAddrAssign_write()
672     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_DAA()  local
686     _i3c_resp_queue_threshold_set(regs, 0);  in MEC_HAL_I3C_DO_DAA()
691     _i3c_command_write(regs, command);  in MEC_HAL_I3C_DO_DAA()
703     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_CCC()  local
740             _i3c_fifo_write(regs, tgt->data_buf, tgt->data_len);  in MEC_HAL_I3C_DO_CCC()
746     _i3c_resp_queue_threshold_set(regs, 0);  in MEC_HAL_I3C_DO_CCC()
751         _i3c_command_write(regs, argument);  in MEC_HAL_I3C_DO_CCC()
756     _i3c_command_write(regs, command);  in MEC_HAL_I3C_DO_CCC()
772     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_Xfer_Prep()  local
821         _i3c_fifo_write(regs, cmd->data_buf, cmd->data_len);  in MEC_HAL_I3C_DO_Xfer_Prep()
830     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_Xfer()  local
833     _i3c_command_write(regs, tgt->arg);  in MEC_HAL_I3C_DO_Xfer()
835     _i3c_command_write(regs, tgt->cmd);  in MEC_HAL_I3C_DO_Xfer()
841     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_TGT_Xfer()  local
847      _i3c_fifo_write(regs, data_buf, data_len);  in MEC_HAL_I3C_DO_TGT_Xfer()
854     _i3c_command_write(regs, command);  in MEC_HAL_I3C_DO_TGT_Xfer()
868     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_IBI_SIR_Enable()  local
878     dat_value = _i3c_DAT_read(regs, ibi_sir_info->DAT_start, ibi_sir_info->tgt_dat_idx);  in MEC_HAL_I3C_IBI_SIR_Enable()
888     _i3c_DAT_write(regs, ibi_sir_info->DAT_start, ibi_sir_info->tgt_dat_idx, dat_value);  in MEC_HAL_I3C_IBI_SIR_Enable()
893         _i3c_intr_IBI_enable(regs);  in MEC_HAL_I3C_IBI_SIR_Enable()
909     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_IBI_SIR_Disable()  local
913     dat_value = _i3c_DAT_read(regs, ibi_sir_info->DAT_start, ibi_sir_info->tgt_dat_idx);  in MEC_HAL_I3C_IBI_SIR_Disable()
918     _i3c_DAT_write(regs, ibi_sir_info->DAT_start, ibi_sir_info->tgt_dat_idx, dat_value);  in MEC_HAL_I3C_IBI_SIR_Disable()
924         _i3c_intr_IBI_disable(regs);  in MEC_HAL_I3C_IBI_SIR_Disable()
936     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_PID_set()  local
938     _i3c_tgt_pid_set(regs, TGT_MIPI_MFG_ID(pid), pid_random,  in MEC_HAL_I3C_TGT_PID_set()
950     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_is_dyn_addr_valid()  local
952     return _i3c_tgt_dyn_addr_valid_get(regs);  in MEC_HAL_I3C_TGT_is_dyn_addr_valid()
962     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_dyn_addr_get()  local
964     return _i3c_tgt_dyn_addr_get(regs);;  in MEC_HAL_I3C_TGT_dyn_addr_get()
981     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_MXDS_set()  local
983     _i3c_tgt_mxds_set(regs, wr_speed, rd_speed, tsco, rd_trnd_us);  in MEC_HAL_I3C_TGT_MXDS_set()
995     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_IBI_SIR_Raise()  local
999     if (_i3c_tgt_SIR_enabled(regs)) {  in MEC_HAL_I3C_TGT_IBI_SIR_Raise()
1002         _i3c_tgt_raise_ibi_SIR(regs, ibi_sir_request->data_buf, ibi_sir_request->data_len,  in MEC_HAL_I3C_TGT_IBI_SIR_Raise()
1019     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_IBI_MR_Raise()  local
1023     if (_i3c_tgt_MR_enabled(regs)) {  in MEC_HAL_I3C_TGT_IBI_MR_Raise()
1026         _i3c_tgt_raise_ibi_MR(regs);  in MEC_HAL_I3C_TGT_IBI_MR_Raise()
1042     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle()  local
1044     _i3c_tx_fifo_rst(regs);  in MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle()
1047     _i3c_resume(regs);  in MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle()
1057     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_Error_Recovery()  local
1064         _i3c_rx_fifo_rst(regs);  in MEC_HAL_I3C_TGT_Error_Recovery()
1069          _i3c_tx_fifo_rst(regs);  in MEC_HAL_I3C_TGT_Error_Recovery()
1070          _i3c_cmd_queue_rst(regs);  in MEC_HAL_I3C_TGT_Error_Recovery()
1073     _i3c_resume(regs);  in MEC_HAL_I3C_TGT_Error_Recovery()
1083     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()  local
1086     _i3c_rx_fifo_rst(regs);  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()
1087     _i3c_tx_fifo_rst(regs);  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()
1090     _i3c_cmd_queue_rst(regs);  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()
1093     _i3c_resume(regs);  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()
1106     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Xfer_Error_Resume()  local
1109     _i3c_resume(regs);  in MEC_HAL_I3C_Xfer_Error_Resume()
1112     _i3c_xfer_err_sts_clr(regs);  in MEC_HAL_I3C_Xfer_Error_Resume()
1122     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Xfer_Reset()  local
1125     _i3c_xfers_reset(regs);  in MEC_HAL_I3C_Xfer_Reset()