83 static uint8_t bbled_get_pwm_size(struct mec_bbled_regs *regs)  in bbled_get_pwm_size()  argument
85     return (uint8_t)((regs->CONFIG & MEC_BBLED_CONFIG_PWM_SZ_Msk) >> MEC_BBLED_CONFIG_PWM_SZ_Pos);  in bbled_get_pwm_size()
88 static void bbled_set_pwm_size(struct mec_bbled_regs *regs, uint8_t pwm_width)  in bbled_set_pwm_size()  argument
90     regs->CONFIG = (regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_PWM_SZ_Msk) |  in bbled_set_pwm_size()
94 static void bbled_set_clk_src(struct mec_bbled_regs *regs, uint8_t use_sys_clk)  in bbled_set_clk_src()  argument
97         regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos);  in bbled_set_clk_src()
99         regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos);  in bbled_set_clk_src()
103 static void bbled_set_wdt_reload(struct mec_bbled_regs *regs, uint32_t bbcfg)  in bbled_set_wdt_reload()  argument
107     regs->CONFIG = ((regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_WDTRLD_Msk) |  in bbled_set_wdt_reload()
111 static void bbled_set_mode(struct mec_bbled_regs *regs, uint8_t mode)  in bbled_set_mode()  argument
113     regs->CONFIG = ((regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_CTRL_Msk) |  in bbled_set_mode()
117 static uint8_t bbled_get_mode(struct mec_bbled_regs *regs)  in bbled_get_mode()  argument
119     return (uint8_t)((regs->CONFIG & MEC_BBLED_CONFIG_CTRL_Msk) >> MEC_BBLED_CONFIG_CTRL_Pos);  in bbled_get_mode()
124 bool mec_hal_bbled_is_valid(struct mec_bbled_regs *regs)  in mec_hal_bbled_is_valid()  argument
126     if (find_bbled_index((uintptr_t)regs) < 0) {  in mec_hal_bbled_is_valid()
133 void mec_hal_bbled_synchronize_enable(struct mec_bbled_regs *regs, uint8_t enable)  in mec_hal_bbled_synchronize_enable()  argument
136         regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_SYNC_Pos);  in mec_hal_bbled_synchronize_enable()
138         regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_SYNC_Pos);  in mec_hal_bbled_synchronize_enable()
142 bool mec_hal_bbled_is_off(struct mec_bbled_regs *regs)  in mec_hal_bbled_is_off()  argument
144     if (regs->CONFIG & MEC_BBLED_CONFIG_CTRL_Msk) {  in mec_hal_bbled_is_off()
151 void mec_hal_bbled_asym_enable(struct mec_bbled_regs *regs, uint8_t enable)  in mec_hal_bbled_asym_enable()  argument
154         regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_ASYM_Pos);  in mec_hal_bbled_asym_enable()
156         regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_ASYM_Pos);  in mec_hal_bbled_asym_enable()
161 int mec_hal_bbled_init(struct mec_bbled_regs *regs, uint32_t bbled_config)  in mec_hal_bbled_init()  argument
163     const struct mec_bbled_info *info = find_bbled_info((uintptr_t)regs);  in mec_hal_bbled_init()
174         regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_SRST_Pos);  in mec_hal_bbled_init()
176         regs->CONFIG &= (uint32_t)~MEC_BBLED_CONFIG_CTRL_Msk;  in mec_hal_bbled_init()
177         regs->CONFIG |= (MEC_BBLED_CONFIG_CTRL_OFF << MEC_BBLED_CONFIG_CTRL_Pos);  in mec_hal_bbled_init()
183         bbled_set_wdt_reload(regs, bbled_config);  in mec_hal_bbled_init()
190     mec_hal_bbled_asym_enable(regs, asym_enable);  in mec_hal_bbled_init()
195 int mec_hal_bbled_girq_ctrl(struct mec_bbled_regs *regs, uint8_t enable)  in mec_hal_bbled_girq_ctrl()  argument
197     const struct mec_bbled_info *info = find_bbled_info((uintptr_t)regs);  in mec_hal_bbled_girq_ctrl()
208 int mec_hal_bbled_girq_status_clr(struct mec_bbled_regs *regs)  in mec_hal_bbled_girq_status_clr()  argument
210     const struct mec_bbled_info *info = find_bbled_info((uintptr_t)regs);  in mec_hal_bbled_girq_status_clr()
221 void mec_hal_bbled_enable_update(struct mec_bbled_regs *regs)  in mec_hal_bbled_enable_update()  argument
223     regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_UPDATE_Pos);  in mec_hal_bbled_enable_update()
226 bool mec_hal_bbled_enable_is_update(struct mec_bbled_regs *regs)  in mec_hal_bbled_enable_is_update()  argument
228     if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_UPDATE_Pos)) {  in mec_hal_bbled_enable_is_update()
235 uint32_t mec_hal_bbled_clk_freq(struct mec_bbled_regs *regs)  in mec_hal_bbled_clk_freq()  argument
237     if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos)) {  in mec_hal_bbled_clk_freq()
243 int mec_hal_bbled_breathe_pwm_width(struct mec_bbled_regs *regs, uint8_t pwm_width)  in mec_hal_bbled_breathe_pwm_width()  argument
247     if (!regs || (pwm_width > MEC_BBLED_PWM_WIDTH_6)) {  in mec_hal_bbled_breathe_pwm_width()
251     mode = bbled_get_mode(regs);  in mec_hal_bbled_breathe_pwm_width()
256     bbled_set_pwm_size(regs, pwm_width);  in mec_hal_bbled_breathe_pwm_width()
261 uint8_t mec_hal_bbled_breathe_pwm_width_get(struct mec_bbled_regs *regs)  in mec_hal_bbled_breathe_pwm_width_get()  argument
263     return bbled_get_pwm_size(regs);  in mec_hal_bbled_breathe_pwm_width_get()
266 int mec_hal_bbled_blink_clk_sel(struct mec_bbled_regs *regs, uint8_t blink_clk_sel)  in mec_hal_bbled_blink_clk_sel()  argument
270     if (!regs) {  in mec_hal_bbled_blink_clk_sel()
278     bbled_set_clk_src(regs, use_sys_clk);  in mec_hal_bbled_blink_clk_sel()
283 uint8_t mec_hal_bbled_blink_clk_sel_get(struct mec_bbled_regs *regs)  in mec_hal_bbled_blink_clk_sel_get()  argument
287     if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos)) {  in mec_hal_bbled_blink_clk_sel_get()
294 uint32_t mec_hal_bbled_blink_pwm_freq_get(struct mec_bbled_regs *regs)  in mec_hal_bbled_blink_pwm_freq_get()  argument
296     uint32_t fsrc = mec_hal_bbled_clk_freq(regs);  in mec_hal_bbled_blink_pwm_freq_get()
297     uint32_t prescaler = (regs->DELAY & MEC_BBLED_DELAY_LO_Msk) >> MEC_BBLED_DELAY_LO_Pos;  in mec_hal_bbled_blink_pwm_freq_get()
313 int mec_hal_bbled_mode(struct mec_bbled_regs *regs, uint8_t mode)  in mec_hal_bbled_mode()  argument
315     if (!regs || (mode > MEC_BBLED_MODE_ON)) {  in mec_hal_bbled_mode()
319     bbled_set_mode(regs, mode);  in mec_hal_bbled_mode()
324 uint8_t mec_hal_bbled_mode_get(struct mec_bbled_regs *regs)  in mec_hal_bbled_mode_get()  argument
326     return bbled_get_mode(regs);  in mec_hal_bbled_mode_get()
329 int mec_hal_bbled_breathe_config(struct mec_bbled_regs *regs, struct mec_bbled_breathe_config *br_c…  in mec_hal_bbled_breathe_config()  argument
334     if (!regs || !br_cfg) {  in mec_hal_bbled_breathe_config()
338     mode = bbled_get_mode(regs);  in mec_hal_bbled_breathe_config()
345     regs->LIMITS = temp;  in mec_hal_bbled_breathe_config()
349     regs->DELAY = temp;  in mec_hal_bbled_breathe_config()
351     regs->UPDSS = br_cfg->upd_steps;  in mec_hal_bbled_breathe_config()
352     regs->UPINVL = br_cfg->upd_intervals;  in mec_hal_bbled_breathe_config()
357 int mec_hal_bbled_breathe_config_get(struct mec_bbled_regs *regs,  in mec_hal_bbled_breathe_config_get()  argument
362     if (!regs || !br_cfg) {  in mec_hal_bbled_breathe_config_get()
366     br_cfg->upd_intervals = regs->UPINVL;  in mec_hal_bbled_breathe_config_get()
367     br_cfg->upd_steps = regs->UPDSS;  in mec_hal_bbled_breathe_config_get()
369     temp = regs->DELAY;  in mec_hal_bbled_breathe_config_get()
373     temp = regs->LIMITS;  in mec_hal_bbled_breathe_config_get()
377     br_cfg->pwm_width = bbled_get_pwm_size(regs);  in mec_hal_bbled_breathe_config_get()
382 int mec_hal_bbled_blink_config(struct mec_bbled_regs *regs, struct mec_bbled_blink_config *bl_cfg)  in mec_hal_bbled_blink_config()  argument
386     if (!regs || !bl_cfg) {  in mec_hal_bbled_blink_config()
390     mode = bbled_get_mode(regs);  in mec_hal_bbled_blink_config()
395     regs->LIMITS =  in mec_hal_bbled_blink_config()
397     regs->DELAY =  in mec_hal_bbled_blink_config()
403 int mec_hal_bbled_blink_config_get(struct mec_bbled_regs *regs, struct mec_bbled_blink_config *bl_c…  in mec_hal_bbled_blink_config_get()  argument
405     if (!regs || !bl_cfg) {  in mec_hal_bbled_blink_config_get()
410         (uint16_t)((regs->DELAY & MEC_BBLED_DELAY_LO_Msk) >> MEC_BBLED_DELAY_LO_Pos);  in mec_hal_bbled_blink_config_get()
412         (uint8_t)((regs->LIMITS & MEC_BBLED_LIMITS_MIN_Msk) >> MEC_BBLED_LIMITS_MIN_Pos);  in mec_hal_bbled_blink_config_get()
414     if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos)) {  in mec_hal_bbled_blink_config_get()