39 int mec_hal_adc_init(struct mec_adc_regs *regs, struct mec_adc_config *cfg)  in mec_hal_adc_init()  argument
45     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_init()
53     regs->CTRL = 0;  in mec_hal_adc_init()
59             regs->CTRL = MEC_BIT(MEC_ADC_CTRL_SRST_Pos);  in mec_hal_adc_init()
61                 if (!(regs->CTRL & MEC_BIT(MEC_ADC_CTRL_SRST_Pos))) {  in mec_hal_adc_init()
65             regs->CTRL = 0;  in mec_hal_adc_init()
69             regs->CTRL |= MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos);  in mec_hal_adc_init()
71             regs->CTRL &= (uint32_t)~MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos);  in mec_hal_adc_init()
79             regs->CONFIG = (regs->CONFIG & (uint32_t)~(MEC_ADC_CONFIG_CLTM_Msk  in mec_hal_adc_init()
85             regs->SAR_CTRL = (regs->SAR_CTRL & (uint32_t)~(MEC_ADC_SAR_CTRL_WARMUPDLY_Msk))  in mec_hal_adc_init()
91             temp = regs->DELAY &  in mec_hal_adc_init()
97             regs->DELAY = (regs->DELAY & (uint32_t)~(MEC_ADC_DELAY_RSTART_DLY_Msk));  in mec_hal_adc_init()
101             regs->SAR_CFG = cfg->sar_config;  in mec_hal_adc_init()
105     regs->CTRL |= MEC_BIT(MEC_ADC_CTRL_ACTV_Pos);  in mec_hal_adc_init()
110 int mec_hal_adc_activate(struct mec_adc_regs *regs, uint8_t enable)  in mec_hal_adc_activate()  argument
115     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_activate()
119     ctrl = regs->CTRL & ~msk;  in mec_hal_adc_activate()
126     regs->CTRL = ctrl;  in mec_hal_adc_activate()
137 int mec_hal_adc_repeat_delay_set(struct mec_adc_regs *regs, uint16_t start_delay,  in mec_hal_adc_repeat_delay_set()  argument
142     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_repeat_delay_set()
146     regs->DELAY = delay;  in mec_hal_adc_repeat_delay_set()
152 int mec_hal_adc_repeat_mode_chan_set(struct mec_adc_regs *regs, uint32_t rpt_chan_bm)  in mec_hal_adc_repeat_mode_chan_set()  argument
154     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_repeat_mode_chan_set()
158     regs->RCHEN = rpt_chan_bm;  in mec_hal_adc_repeat_mode_chan_set()
163 int mec_hal_adc_chan_vref_select(struct mec_adc_regs *regs, uint8_t chan_id,  in mec_hal_adc_chan_vref_select()  argument
166     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_chan_vref_select()
174     uint32_t temp = regs->VREF_CHAN;  in mec_hal_adc_chan_vref_select()
178     regs->VREF_CHAN = temp;  in mec_hal_adc_chan_vref_select()
183 int mec_hal_adc_differential_input_enable(struct mec_adc_regs *regs, uint8_t enable)  in mec_hal_adc_differential_input_enable()  argument
185     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_differential_input_enable()
190         regs->SAR_CTRL |= MEC_BIT(MEC_ADC_SAR_CTRL_SELDIFF_Pos);  in mec_hal_adc_differential_input_enable()
192         regs->SAR_CTRL &= (uint32_t)~MEC_BIT(MEC_ADC_SAR_CTRL_SELDIFF_Pos);  in mec_hal_adc_differential_input_enable()
198 int mec_hal_adc_resolution_set(struct mec_adc_regs *regs, uint8_t resolution_bits)  in mec_hal_adc_resolution_set()  argument
202     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_resolution_set()
217     regs->SAR_CTRL = (regs->SAR_CTRL & (uint32_t)~(MEC_ADC_SAR_CTRL_SELRES_Msk))  in mec_hal_adc_resolution_set()
223 int mec_hal_adc_girq_ctrl(struct mec_adc_regs *regs, uint32_t flags, uint8_t enable)  in mec_hal_adc_girq_ctrl()  argument
227     if (!regs) {  in mec_hal_adc_girq_ctrl()
237 int mec_hal_adc_girq_status_clr(struct mec_adc_regs *regs, uint32_t flags)  in mec_hal_adc_girq_status_clr()  argument
241     if (!regs) {  in mec_hal_adc_girq_status_clr()
251 uint32_t mec_hal_adc_channels_done(struct mec_adc_regs *regs)  in mec_hal_adc_channels_done()  argument
253     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_channels_done()
257     return regs->STATUS;  in mec_hal_adc_channels_done()
260 uint32_t mec_hal_adc_channel_reading(struct mec_adc_regs *regs, uint8_t channel)  in mec_hal_adc_channel_reading()  argument
262     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_channel_reading()
270     return regs->RD[channel];  in mec_hal_adc_channel_reading()
279 int mec_hal_adc_status_clear(struct mec_adc_regs *regs, uint32_t flags)  in mec_hal_adc_status_clear()  argument
283     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_status_clear()
288         regs->STATUS |= regs->SCHEN;  in mec_hal_adc_status_clear()
294         regs->STATUS |= regs->RCHEN;  in mec_hal_adc_status_clear()
299     regs->CTRL |= ctrl_val;  in mec_hal_adc_status_clear()
306 int mec_hal_adc_start(struct mec_adc_regs *regs, uint16_t single_chan_bm, uint16_t rpt_chan_bm)  in mec_hal_adc_start()  argument
310     if ((uintptr_t)regs != (uintptr_t)MEC_ADC0_BASE) {  in mec_hal_adc_start()
318         regs->SCHEN = single_chan_bm;  in mec_hal_adc_start()
325         regs->RCHEN = rpt_chan_bm;  in mec_hal_adc_start()
329         regs->STATUS = single_chan_bm | rpt_chan_bm;  in mec_hal_adc_start()
330         regs->CTRL |= ctrl_sts;  in mec_hal_adc_start()
332         regs->CTRL |= start_val;  in mec_hal_adc_start()