Lines Matching refs:regs
578 uint32_t _i3c_intr_sts_get(struct mec_i3c_host_regs *regs);
579 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask);
580 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
581 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
582 void _i3c_intr_IBI_enable(struct mec_i3c_host_regs *regs);
583 void _i3c_intr_IBI_disable(struct mec_i3c_host_regs *regs);
585 void _i3c_resp_buf_threshold_set(struct mec_i3c_host_regs *regs, uint8_t threshold);
586 void _i3c_cmd_queue_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
587 void _i3c_tx_fifo_empty_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
588 void _i3c_rx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
589 void _i3c_tx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
590 void _i3c_tx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
591 void _i3c_rx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
593 void _i3c_notify_sir_reject(struct mec_i3c_host_regs *regs, bool opt);
594 void _i3c_notify_mr_reject(struct mec_i3c_host_regs *regs, bool opt);
595 void _i3c_notify_hj_reject(struct mec_i3c_host_regs *regs, bool opt);
597 void _i3c_resp_queue_threshold_set(struct mec_i3c_host_regs *regs, uint8_t threshold);
598 void _i3c_cmd_queue_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
599 void _i3c_ibi_data_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
600 void _i3c_ibi_status_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
601 uint32_t _i3c_ibi_queue_status_get(struct mec_i3c_host_regs *regs);
603 void _i3c_dynamic_addr_set(struct mec_i3c_host_regs *regs, uint8_t address);
604 void _i3c_static_addr_set(struct mec_i3c_host_regs *regs, uint8_t address);
606 void _i3c_operation_mode_set(struct mec_i3c_host_regs *regs, uint8_t mode);
608 void _i3c_hot_join_disable(struct mec_i3c_host_regs *regs);
609 void _i3c_hot_join_enable(struct mec_i3c_host_regs *regs);
612 void _i3c_ibi_cm_req_reject(struct mec_i3c_host_regs *regs);
613 void _i3c_ibi_tm_intr_req_reject(struct mec_i3c_host_regs *regs);
615 void _i3c_enable(struct mec_i3c_host_regs *regs, uint8_t mode, bool enable_dma);
616 void _i3c_disable(struct mec_i3c_host_regs *regs);
617 void _i3c_resume(struct mec_i3c_host_regs *regs);
619 void _i3c_push_pull_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns,
622 void _i3c_open_drain_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns,
625 void _i3c_bus_free_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns);
626 void _i3c_bus_available_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns);
627 void _i3c_bus_idle_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns);
628 void _i3c_read_term_bit_low_count_set(struct mec_i3c_host_regs *regs,
630 void _i3c_sda_hld_timing_set(struct mec_i3c_host_regs *regs,
632 void _i3c_sda_hld_switch_delay_timing_set(struct mec_i3c_sec_regs *regs,
636 void _i3c_scl_low_mst_tout_set(struct mec_i3c_sec_regs *regs, uint32_t tout_val);
638 void _i2c_fm_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns);
639 void _i2c_fmp_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns);
640 void _i2c_target_present_set (struct mec_i3c_host_regs *regs);
641 void _i2c_target_present_reset (struct mec_i3c_host_regs *regs);
643 void _i3c_host_dma_tx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val);
644 void _i3c_host_dma_rx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val);
645 void _i3c_host_port_set(struct mec_i3c_host_regs *regs, uint32_t val);
646 void _i3c_host_stuck_sda_config(struct mec_i3c_host_regs *regs, uint32_t val,
648 void _i3c_host_tx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t val,
650 void _i3c_host_rx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t val,
653 void _i3c_sec_host_dma_tx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val);
654 void _i3c_sec_host_dma_rx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val);
655 void _i3c_sec_host_port_set(struct mec_i3c_sec_regs *regs, uint32_t val);
656 void _i3c_sec_host_stuck_sda_scl_config(struct mec_i3c_sec_regs *regs, uint32_t en,
658 void _i3c_sec_host_tx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t val,
660 void _i3c_sec_host_rx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t val,
662 void _i3c_sec_host_dma_fsm_enable(struct mec_i3c_sec_regs *regs);
664 void _i3c_dev_addr_table_ptr_get(struct mec_i3c_host_regs *regs, uint16_t *start_addr,
666 void _i3c_dev_char_table_ptr_get(struct mec_i3c_host_regs *regs, uint16_t *start_addr,
669 uint8_t _i3c_dev_operation_mode_get(struct mec_i3c_host_regs *regs);
671 uint8_t _i3c_dev_controller_role_get(struct mec_i3c_host_regs *regs);
673 uint8_t _i3c_dev_role_config_get(struct mec_i3c_host_regs *regs);
675 void _i3c_DAT_write(struct mec_i3c_host_regs *regs, uint16_t DAT_start, uint8_t DAT_idx,
677 uint32_t _i3c_DAT_read(struct mec_i3c_host_regs *regs, uint16_t DAT_start, uint8_t DAT_idx);
678 void _i3c_DCT_read(struct mec_i3c_host_regs *regs, uint16_t DCT_start, uint8_t DCT_idx,
681 void _i3c_fifo_write(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len);
682 void _i3c_command_write(struct mec_i3c_host_regs *regs, uint32_t cmd);
684 uint8_t _i3c_resp_buf_level_get(struct mec_i3c_host_regs *regs);
685 uint8_t _i3c_ibi_status_count_get(struct mec_i3c_host_regs *regs);
687 uint8_t _i3c_response_sts_get(struct mec_i3c_host_regs *regs, uint16_t *len, uint8_t *tid);
688 void _i3c_fifo_read(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len);
689 void _i3c_ibi_data_read(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len);
691 void _i3c_xfers_reset(struct mec_i3c_host_regs *regs);
692 void _i3c_soft_reset(struct mec_i3c_host_regs *regs);
694 void _i3c_xfer_err_sts_clr(struct mec_i3c_host_regs *regs);
696 uint8_t _i3c_cmd_fifo_depth_get(struct mec_i3c_host_regs *regs);
697 uint8_t _i3c_tx_fifo_depth_get(struct mec_i3c_host_regs *regs);
698 uint8_t _i3c_rx_fifo_depth_get(struct mec_i3c_host_regs *regs);
699 uint8_t _i3c_resp_fifo_depth_get(struct mec_i3c_host_regs *regs);
700 uint8_t _i3c_ibi_fifo_depth_get(struct mec_i3c_host_regs *regs);
703 void _i3c_tx_fifo_rst(struct mec_i3c_host_regs *regs);
704 void _i3c_rx_fifo_rst(struct mec_i3c_host_regs *regs);
705 void _i3c_cmd_queue_rst(struct mec_i3c_host_regs *regs);
707 void _i3c_SDCT_read(struct mec_i3c_host_regs *regs, uint16_t DCT_start, uint8_t DCT_idx,
710 void _i3c_intr_thresholds_tx_enable(struct mec_i3c_host_regs *regs);
711 void _i3c_intr_thresholds_tx_disable(struct mec_i3c_host_regs *regs);
712 void _i3c_intr_thresholds_rx_enable(struct mec_i3c_host_regs *regs);
713 void _i3c_intr_thresholds_rx_disable(struct mec_i3c_host_regs *regs);
717 void _i3c_tgt_pid_set(struct mec_i3c_sec_regs *regs,
723 bool _i3c_tgt_dyn_addr_valid_get(struct mec_i3c_sec_regs *regs);
724 uint8_t _i3c_tgt_dyn_addr_get(struct mec_i3c_sec_regs *regs);
725 void _i3c_tgt_mrl_set(struct mec_i3c_sec_regs *regs, uint16_t mrl);
726 void _i3c_tgt_mwl_set(struct mec_i3c_sec_regs *regs, uint16_t mwl);
727 void _i3c_tgt_mxds_set(struct mec_i3c_sec_regs *regs,
732 bool _i3c_tgt_SIR_enabled(struct mec_i3c_sec_regs *regs);
733 bool _i3c_tgt_MR_enabled(struct mec_i3c_sec_regs *regs);
734 void _i3c_tgt_raise_ibi_SIR(struct mec_i3c_sec_regs *regs, uint8_t *sir_data, uint8_t sir_datalen,
736 void _i3c_tgt_raise_ibi_MR(struct mec_i3c_sec_regs *regs);
737 bool _i3c_tgt_ibi_resp_get(struct mec_i3c_sec_regs *regs, uint8_t *sir_rem_datalen);
739 uint8_t _i3c_tgt_response_sts_get(struct mec_i3c_sec_regs *regs, uint16_t *len, uint8_t *tid,
742 void _i3c_tgt_MRL_get(struct mec_i3c_sec_regs *regs, uint16_t *max_rd_len);
743 void _i3c_tgt_MWL_get(struct mec_i3c_sec_regs *regs, uint16_t *max_wr_len);
744 void _i3c_tgt_MRL_MWL_set(struct mec_i3c_sec_regs *regs, uint16_t max_rd_len,
747 bool _i3c_tgt_MRL_updated(struct mec_i3c_sec_regs *regs);
748 bool _i3c_tgt_MWL_updated(struct mec_i3c_sec_regs *regs);
749 void _i3c_tgt_hot_join_disable(struct mec_i3c_sec_regs *regs);
751 void _i3c_tgt_max_speed_update(struct mec_i3c_sec_regs *regs, uint8_t max_rd_speed,
753 void _i3c_tgt_clk_to_data_turn_update(struct mec_i3c_sec_regs *regs, uint8_t clk_data_turn_time);