29 static void peci_reset(struct mec_peci_regs *regs)  in peci_reset()  argument
31     regs->CTRL = (MEC_BIT(MEC_PECI_CTRL_RST_Pos) | MEC_BIT(MEC_PECI_CTRL_FRST_Pos)  in peci_reset()
33     regs->IEN1 = 0u;  in peci_reset()
34     regs->IEN2 = 0u;  in peci_reset()
35     regs->STATUS1 = UINT8_MAX;  in peci_reset()
36     regs->STATUS1 = UINT8_MAX;  in peci_reset()
37     regs->CTRL = MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos);  in peci_reset()
46 static void peci_intr_en(struct mec_peci_regs *regs, uint16_t ien_bitmap)  in peci_intr_en()  argument
52     regs->IEN1 |= (uint8_t)(ien_bitmap & 0xffu);  in peci_intr_en()
53     regs->IEN2 |= (uint8_t)((ien_bitmap >> 8) & 0xffu);  in peci_intr_en()
59 int mec_hal_peci_init(struct mec_peci_regs *regs, struct mec_peci_config *cfg, uint32_t flags)  in mec_hal_peci_init()  argument
62     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_init()
75         peci_reset(regs);  in mec_hal_peci_init()
82         regs->BAUD_CTRL = cfg->clock_div;  in mec_hal_peci_init()
86         regs->OPTBTM_LO = (uint8_t)(cfg->optimal_bit_time);  in mec_hal_peci_init()
87         regs->OPTBTM_HI = (uint8_t)(cfg->optimal_bit_time >> 8);  in mec_hal_peci_init()
91         regs->REQ_TIMER_LSB = (uint8_t)(cfg->request_timer);  in mec_hal_peci_init()
92         regs->REQ_TIMER_MSB = (uint8_t)(cfg->request_timer >> 8);  in mec_hal_peci_init()
96         regs->SSTCTL1 |= MEC_BIT(MEC_PECI_SSTCTL1_DNBTC_Pos);  in mec_hal_peci_init()
102         peci_intr_en(regs, cfg->intr_enables);  in mec_hal_peci_init()
103         regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_MIEN_Pos);  in mec_hal_peci_init()
107         regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos);  in mec_hal_peci_init()
113 int mec_hal_peci_enable(struct mec_peci_regs *regs, uint8_t enable)  in mec_hal_peci_enable()  argument
116     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_enable()
122         regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos);  in mec_hal_peci_enable()
124         regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos);  in mec_hal_peci_enable()
130 int mec_hal_peci_ctrl_reset(struct mec_peci_regs *regs, uint8_t assert_reset)  in mec_hal_peci_ctrl_reset()  argument
133     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_ctrl_reset()
139         regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_RST_Pos);  in mec_hal_peci_ctrl_reset()
141         regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_RST_Pos);  in mec_hal_peci_ctrl_reset()
147 int mec_hal_peci_fifo_reset(struct mec_peci_regs *regs, uint8_t assert_reset)  in mec_hal_peci_fifo_reset()  argument
150     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_fifo_reset()
156         regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_FRST_Pos);  in mec_hal_peci_fifo_reset()
158         regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_FRST_Pos);  in mec_hal_peci_fifo_reset()
167 int mec_hal_peci_global_ien(struct mec_peci_regs *regs, uint8_t enable)  in mec_hal_peci_global_ien()  argument
170     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_global_ien()
176         regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_MIEN_Pos);  in mec_hal_peci_global_ien()
178         regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_MIEN_Pos);  in mec_hal_peci_global_ien()
187 int mec_hal_peci_intr_ctrl(struct mec_peci_regs *regs, uint8_t enable, uint16_t intr_bitmap)  in mec_hal_peci_intr_ctrl()  argument
190     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_intr_ctrl()
196         regs->IEN1 |= (uint8_t)intr_bitmap;  in mec_hal_peci_intr_ctrl()
197         regs->IEN2 |= (uint8_t)(intr_bitmap >> 8);  in mec_hal_peci_intr_ctrl()
199         regs->IEN1 &= (uint8_t)~intr_bitmap;  in mec_hal_peci_intr_ctrl()
200         regs->IEN2 &= (uint8_t)~(intr_bitmap >> 8);  in mec_hal_peci_intr_ctrl()
206 int mec_hal_peci_set_opt_bit_time(struct mec_peci_regs *regs, uint16_t opt_bit_time)  in mec_hal_peci_set_opt_bit_time()  argument
209     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_set_opt_bit_time()
218     uint8_t ctrl = regs->CTRL;  in mec_hal_peci_set_opt_bit_time()
220     regs->CTRL = ctrl | MEC_BIT(MEC_PECI_CTRL_PWRDN_Pos);  in mec_hal_peci_set_opt_bit_time()
221     regs->OPTBTM_LO = (uint8_t)opt_bit_time;  in mec_hal_peci_set_opt_bit_time()
222     regs->OPTBTM_HI = (uint8_t)(opt_bit_time >> 8);  in mec_hal_peci_set_opt_bit_time()
223     regs->CTRL = ctrl;  in mec_hal_peci_set_opt_bit_time()
231 int mec_hal_peci_tx_enable(struct mec_peci_regs *regs, uint8_t enable)  in mec_hal_peci_tx_enable()  argument
234     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_tx_enable()
240         regs->CTRL |= MEC_BIT(MEC_PECI_CTRL_TXEN_Pos);  in mec_hal_peci_tx_enable()
242         regs->CTRL &= (uint8_t)~MEC_BIT(MEC_PECI_CTRL_TXEN_Pos);  in mec_hal_peci_tx_enable()
248 uint32_t mec_hal_peci_status(struct mec_peci_regs *regs)  in mec_hal_peci_status()  argument
251     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_status()
256     uint32_t sts = regs->STATUS1;  in mec_hal_peci_status()
258     sts |= ((uint32_t)regs->STATUS2 << 8);  in mec_hal_peci_status()
259     sts |= ((uint32_t)regs->ERROR << 16);  in mec_hal_peci_status()
268 uint32_t mec_hal_peci_status_clear(struct mec_peci_regs *regs, uint32_t sts)  in mec_hal_peci_status_clear()  argument
271     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_status_clear()
276     regs->ERROR = (uint8_t)(sts >> 16);  in mec_hal_peci_status_clear()
277     regs->STATUS1 = (uint8_t)sts;  in mec_hal_peci_status_clear()
282 int mec_hal_peci_girq_en(struct mec_peci_regs *regs)  in mec_hal_peci_girq_en()  argument
285     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_girq_en()
289     (void)regs;  in mec_hal_peci_girq_en()
297 int mec_hal_peci_girq_dis(struct mec_peci_regs *regs)  in mec_hal_peci_girq_dis()  argument
300     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_girq_dis()
304     (void)regs;  in mec_hal_peci_girq_dis()
312 int mec_hal_peci_girq_clr(struct mec_peci_regs *regs)  in mec_hal_peci_girq_clr()  argument
315     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_girq_clr()
319     (void)regs;  in mec_hal_peci_girq_clr()
327 uint32_t mec_hal_peci_girq_result(struct mec_peci_regs *regs)  in mec_hal_peci_girq_result()  argument
330     if ((uintptr_t)regs != (uintptr_t)MEC_PECI0_BASE) {  in mec_hal_peci_girq_result()
334     (void)regs;  in mec_hal_peci_girq_result()